Example Design Options Tab - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

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1.0 English

The following figure shows the Example Design Options tab for the HBM IP.

Figure 1. AXI HBM Customize IP – Example Design Options Tab
Clocking for AXI Masters
Specifies the AXI clock frequency to be used for all enabled AXI interfaces in Example Design. The MMCM primitive is instantiated per stack in the example design top level file to generate the AXI clock. The ‘AXI Clock Frequency (MHz)’ specifies the MMCM output clock frequency that is used as AXI clock for all AXI interfaces. The ‘AXI Input Clock Frequency (MHz)’ specifies the MMCM input clock frequency.
Select to add VIO instance in the example design. These VIOs can be use to start or pause traffic for the Synthesizable Traffic Generator, report any data miscompares, as well as track the number of Write and Read transactions:
  • vio_tg_start_x - Start traffic on AXI Port X
  • vio_tg_pause_x - Pause traffic on AXI Port X
  • axi_x_data_msmatch_err - Data error reported on AXI Port X
  • wr_cnt_x - Write transaction count on AXI Port X
  • rd_cnt_x - Read transaction count on AXI Port X
Example TG for Simulation
Select a Traffic Generator module to be used in the Simulation flow. Default selection of TG for simulation flow is Non-Synthesizable TG. The Non-Synthesizable TG allows for a text based pattern entry for easy pattern generation. This is described in more detail in the Non-Synthesizable Traffic Generator section. Drop down option is provided to select 'Synthesizable TG' for a more traditional RTL stimulus which is described in more detail in the Synthesizable Traffic Generator section. The Synthesizable Traffic Generator is always present in fully implemented hardware designs.