HBM Configuration Selection Tab - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

Document ID
PG276
Release Date
2021-08-06
Version
1.0 English

The following figure shows the Customize IP dialog box for HBM IP with the HBM Configuration Selection tab.

Figure 1. AXI HBM Customize IP – HBM Configuration Selection Tab
Component Name
The component name is used as the base name of output files generated for the module. Names must begin with a letter and must be composed from characters: a to z, 0 to 9, and "_".
Controller/PHY Mode
Select between a complete Controller and Physical Layer option or a Physical Layer Only design.
HBM Density
Selects 1 or 2 memory stacks to be configured. After selecting the memory density, the Total Available Memory field underneath updates accordingly. The settings in the MC Stack sub-tab also affects the memory value displayed.
Stack Select
Selects physical location (LEFT/RIGHT) of a Single Stack configuration. After selecting the physical location of the stack, the LOC constrains are modified in the IP XDC accordingly.
Total Available Memory (MB)
Displays the total available memory based on the HBM Density as well as the number of memory channels enabled.
Enable Switch (0/1)/Global Addressing Stack (0/1)
Select this to enable Global Addressing. If the total available memory is selected for the HBM Density, then a duplicate option for Stack 1 appears. Selecting this option allows the flexibility of global addressing at the cost of latency. If this is disabled, each AXI port can only access the pseudo channel assigned to it. See Table 2
Enable and Configure all MCs to Same Value
Selecting Yes sets all Memory Channels to the same value. All the options in the GUI references MC0 and all MC0 settings are applied to all enabled Memory Channels. Selecting No for this option displays options for each Memory Channel.
Enable External APB Interface
Enable the external APB interface to Write/read the documented controller status and performance registers.

Clocking

HBM Frequency for Stack 0/1 (MHz)
Specifies the memory interface clock (ck_t) frequency. The wizard internally generates the necessary PLL settings to generate this memory clock frequency. The supported range is shown in Figure 1.
PLL Reference Input Clock (MHz)
Specifies the PLL reference clock frequency that the core uses to generate the HBM clock.
APB Interface 0/1 Clock (MHz)
Specifies the register interface (APB) clock frequency. This frequency should match with the exact frequency driven on APB_PCLK_* port. The supported range is shown in Figure 1.
Temperature Polling Interval on APB-0/1 (ms)
Specifies the interval at which the temperature sensor is read internally and output on the DRAM_x_STATE_TEMP port. The interval is specified in milliseconds.

Select MCs to Enable for Stack 0/1

The MC Stack tab lists all the Memory Channel controllers in each stack, and each might be individually enabled or disabled for power savings.

Tip: Disabling MCs also disables the memory underneath. This is not the same as not using one of the 16 available AXI interfaces.

Select AXI Slaves to Enable for Stack 0/1

The AXI Slaves section lists all the possible AXI ports which can be used in the stack depending on the Global Address option and the enabled MCs.

Switch Clock Select 0/1

Select the clock to use for the AXI Switch. The IP automatically defaults to a clock that is roughly in the middle of the enabled Memory Channels. For each Memory Channel there are two AXI ports available. If Memory Channels 0, 2, 3, and 7 are enabled this means that AXI ports 0, 1 (for MC0), 4, 5 (for MC2), 6, 7 (for MC3), 14, and 15 (for MC7) are enabled and might be selected to use for the Switch Clock.

Select Line Rate for Each MC of Stack 0/1

Selects the memory channel operating frequency. This setting is automatically updated based on the IP configuration and is for information only.