HBM Reordering Options - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

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1.0 English

The HBM IP has many reordering and refresh options available in the Reorder, Refresh, and Power Savings options page in the Vivado IDE. When the default Row Bank Column address map option is used you can select from the different reordering options. However, when the Custom Address Map option is selected, many of the reordering options are disabled, except for the Disable Dynamic Open Page option, but the Refresh and Power Savings Options remain. This is due to dependencies within the reordering core logic and the HBM controller. To make the best use of the reordering options with the default address map it is necessary to understand the functional and performance implications for each of these.

The HBM solution has two levels of command reordering. The HBM memory controller itself has a 12-entry deep command queue where it uses look ahead logic to optimize for the current state of the HBM memory arrays and the pending commands. This is enabled by default and functions like any other look ahead logic within a DDR controller.

The other level of reordering is a 64-entry deep AXI command queue which is available with the default Row Bank Column address map. This can be used by selecting the Enable Request Reordering option in the HBM configuration options in the Vivado IDE. It interacts with the Enable Coherency in Reordering, Reorder Queue Age Limit, and Enable Close Page Reorder options. When enabled the AXI command queue operates similarly to the standard reordering logic in a DDR controller. The logic targets already open Bank/Row combinations to increase the page hit rate. Accesses to different Bank Groups are promoted over accesses to the same Bank Group. If the controller can issue an Activate immediately, these are promoted over accesses which require a Precharge before they can be activated. Read/Write accesses are coalesced when possible to reduce bus turnaround.

In a case where data coherency is not guaranteed by the user traffic masters, using the Enable Coherency in Reordering option ensures that accesses with Bank/Row locality are executed in the order they are received. If the system has latency limitations when Request Reordering is enabled, the Reorder Queue Age Limit option can be decreased from the default value of 128. This value means that up to 128 new commands can be serviced before a pending command is bumped to the top of the queue. The Enable Closed Page Reorder option turns any command in the queue to an Auto-Precharge operation. This means that every Write or Read access causes a new Bank activation because each command is marked as Auto-Precharge. This option is useful if the access pattern has short bursts with highly random addressing.

When evaluating system performance through simulation or in hardware, it is important to note the implications when the AXI reordering queue is enabled. Firstly, the traffic pattern sequence needs to be sufficiently long for the controller to enter steady state operation. If your Write sequence is too short, you might see overly optimistic performance because the controller is consuming the incoming commands without any backpressure. The opposite is true for the Read sequence. If too few commands are issued the Read performance appears to be low because most of the time is being spent on protocol overhead rather than data transfer. When evaluating latency with the reordering queue enabled it is important to model an access pattern which matches the user application and is sufficiently long, especially with mixed traffic, to see if the Reorder Queue Age Limit needs to be adjusted. A good starting point for this analysis would be a run time which covers 10 refresh cycles, or about 40 μs.

Within the HBM memory controller you can change the look ahead behavior as well as the open or closed page policy of the controller. By default the Look Ahead Precharge and Activate options are enabled and this follows the same concepts seen in standard DDR controllers. When these options are enabled the controller considers the current state of the memory array as well as the pending 12 commands in the queue, and inserts Precharge or Activate commands opportunistically. The Disable Dynamic Open Page option forces the controller to keep a currently active Row/Bank open until there is a discrete command to the target Bank which requires a Row change. This is the Precharge and Activate sequence. This might be helpful for low bandwidth traffic streams with a high level of locality in the memory array.