HBM Topology - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

Document ID
PG276
Release Date
2021-08-06
Version
1.0 English

The Xilinx HBM solutions are available in either 4 GB or 8 GB per stack options, with nearly all configurations containing two stacks per FPGA. This means there is a total of 8 GB or 16 GB of available memory for these dual stack devices.

The total data-bit width of an HBM stack is 1024 bits divided across eight channels of 128 bits each. Each channel is serviced by a single memory controller which accesses the HBM in pseudo channel mode, meaning two semi-independent 64-bit data channels with a shared command/address/control (CAC) bus. A 4 GB per stack device has 4 Gb per channel, and each channel has two 2 Gb or 256 MB pseudo channels. An 8 GB per stack device has 8 Gb per channel, and each channel has two 4 Gb or 512 MB pseudo channels.

Most of the HBM protocol requirements and timing can be evaluated on a pseudo channel basis, meaning that two Activate commands can be issued back to back to PC0 and PC1 without considering tRRD. If two Activate commands are issued to the same pseudo channel back to back, tRRD must first expire before the second Activate command can be issued.

The HBM always operates with a burst length of 4 in pseudo channel mode. The HBM protocol closely matches that of DDR4 memory, so many of the same performance and protocol concepts apply. The clock rate of the HBM is set in the IP configuration options in the Vivado IDE. HBM is a double data rate (DDR) memory, so the data bus toggles at twice the interface clock rate.