Hardware Manager - HBM Debug Interface - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

Document ID
PG276
Release Date
2021-08-06
Version
1.0 English

The Xilinx® Vivado® hardware manager has a customized interface for UltraScale+™ devices utilizing the integrated HBM. This interface has a configuration view for verifying the IP settings as well as a dynamic graph for tracking performance through the activity monitor registers present in the memory controller. This interface requires the 'Enable Hardware Debug Interface' option to be set in the HBM IP. If the option is not set, the HBM will not appear in the Debug core list.

Note: When any IP containing a debug core is used, the Vivado tools will automatically select a clock for the master debug hub. To manually specify a clock, use the connect_debug_port constraint. The following is the constraint that is used in the HBM example design.

connect_debug_port dbg_hub/clk [get_nets */APB_0_PCLK]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]