IP Facts - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

Document ID
Release Date
1.0 English
LogiCORE IP Facts Table
Core Specifics
Supported Device Family 1 Virtex® UltraScale+™ HBM Devices
Supported User Interfaces AXI3, AMBA APB
Resources N/A
Provided with Core
Design Files Encrypted RTL
Example Design Verilog
Test Bench Verilog AXI Traffic Generator
Constraints File Provided
Simulation Model Encrypted Verilog
Supported S/W Driver N/A
Tested Design Flows 2
Design Entry Vivado® Design Suite
Simulation (3) (4) Simulation is supported with Verilog Compliler Simulator (VCS), Incisive Enterprise Simulator (IES), and Questa Advanced Simulator. For supported simulator versions, see Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Release Notes and Known Issues Master Answer Record: 69267
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Provided by Xilinx® at the Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado IP catalog.
  2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.
  3. Behavioral simulations using verilog simulation models are supported. Netlist (post-synthesis and post-implementation) simulations are not supported.
  4. Simulations in 32-bit environments are not recommended due to the limitation of addressable system memory.