Implementing the Example Design - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

Document ID
PG276
Release Date
2021-08-06
Version
1.0 English
  1. Select the HBM IP from the Vivado IP catalog as shown in the following figure.
  2. Choose the IP settings and click OK.
  3. Under the Synthesis Options, select the Global option and click Generate.
  4. Right-click the HBM IP and select, the following window appears Open IP Example Design.
  5. A new project opens, under the Project Manager, select Settings and click Simulation.
  6. In the Project Settings under Simulation, select Verilog Compiler Simulator (VCS) as the Target simulator as shown in the following figure.
  7. Change the Compiled library location to the location of the compiled library in the installation area.
  8. In the Simulation tab, in the vcs.simulate.vcs.more_options enter +notimingcheck.
    1. For Questa simulator: In the Compilation tab questa.compile.vlog.more_options add +notimingchecks

      In the Simulation tab questa.simulate.vsim.more_options add +notimingchecks as well.

      Also in the Simulation tab questa.simulate.vsim.more_options add -onfinish final. This executes the final block specified by any module when simulation ends.

    2. For IES simulator, add -notimingchecks in the Elaboration tab ies.elaboration.ncelab.more_options.
  9. In the Simulation tab, change the run-time to 1 ms as shown in the following figure.
  10. Run the simulation.