Memory Controller Register Map - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

Document ID
PG276
Release Date
2021-08-06
Version
1.0 English

The HBM memory controller configuration and status registers are accessible using an APB port. There is one APB port per stack and the 22-bit address space is not shared between stacks. The address space is segmented into individual regions which are addressed by the most significant five bits. The remaining 17 bits address the local space within the region. The _PS0 and _PS1 suffix in the register name denote the pseudo channel within the selected memory controller.

Table 1. Region Addressing
Upper 5 bit address Region Name
01000 Memory Controller 0
01100 Memory Controller 1
01001 Memory Controller 2
01101 Memory Controller 3
01010 Memory Controller 4
01110 Memory Controller 5
01011 Memory Controller 6
01111 Memory Controller 7
Table 2. ECC and Status Registers
Register Name Lower 17 bit Address Definition
CFG_ECC_CORRECTION_EN 0x05800 D0 : Set this bit to correct 1-bit errors and detect 2-bit errors. Reset value is 1'b1.
INIT_ECC_SCRUB_EN 0x05804 D0 : If this bit is set, and if CFG_ECC_CORRECTION_EN is also set, then ECC scrubbing is enabled for all addresses in this memory controller. Single bit errors will be detected and corrected. Double bit errors will be detected.
CFG_ECC_SCRUB_PERIOD 0x05810 D[12..0] : Period between read operations for ECC scrubbing. This value is in units of 256 memory clock periods. A value of 0x02 means 512 memory clock periods between each read. Reset value is 13'h02.
INIT_WRITE_DATA_1B_ECC_ERROR_GEN_PS0 0x0584c D[3..0] : Setting one of these bits will instruct the Memory Controller to insert a single 1-bit ECC error on the next cycle of write data. The enabled bit selects which write of the BL4 has the error. For additional error generation, the bit must be reset then set again. Reset value is 4'h0.
INIT_WRITE_DATA_2B_ECC_ERROR_GEN_PS0 0x05850 D[3..0] : Setting one of these bits will instruct the Memory Controller to insert a single 2-bit ECC error on the next cycle of write data. The enabled bit selects which write of the BL4 has the error. For additional error generation, the bit must be reset then set again. Reset value is 4'h0.
INIT_WRITE_DATA_1B_ECC_ERROR_GEN_PS1 0x05854 D[3..0] : Setting one of these bits will instruct the Memory Controller to insert a single 1-bit ECC error on the next cycle of write data. The enabled bit selects which write of the BL4 has the error. For additional error generation, the bit must be reset then set again. Reset value is 4'h0.
INIT_WRITE_DATA_2B_ECC_ERROR_GEN_PS1 0x05858 D[3..0] : Setting one of these bits will instruct the Memory Controller to insert a single 2-bit ECC error on the next cycle of write data. The enabled bit selects which write of the BL4 has the error. For additional error generation, the bit must be reset then set again. Reset value is 4'h0.
STAT_ECC_ERROR_1BIT_CNT_PS0 0x05828 D[7..0] : A counter that increments whenever 1-bit ECC errors have been detected. Holds the value when maximum count has been reached (255) or until reset by INIT_ECC_ERROR_CLR. Reset value 8’b0.
STAT_ECC_ERROR_1BIT_CNT_PS1 0x05834 D[7..0] : A counter that increments whenever 1-bit ECC errors have been detected. Holds the value when maximum count has been reached (255) or until reset by INIT_ECC_ERROR_CLR. Reset value 8’b0
STAT_ECC_ERROR_2BIT_CNT_PS0 0x0582C D[7..0] : A counter that increments whenever 2-bit ECC errors have been detected. Holds the value when maximum count has been reached (255) or until reset by INIT_ECC_ERROR_CLR. Reset value 8’b0.
STAT_ECC_ERROR_2BIT_CNT_PS1 0x05838 D[7..0] : A counter that increments whenever 2-bit ECC errors have been detected. Holds the value when maximum count has been reached (255) or until reset by INIT_ECC_ERROR_CLR. Reset value 8’b0
INIT_ECC_ERROR_CLR 0x05818 D[0] : When set to 1 this will reset the STAT_ECC_ERR_1BIT_CNT_PSx registers. When set to 0 the counters will resume. Reset value 1’b0.
CFG_ECC_1BIT_INT_THRESH 0x0585C D[7..0] : This register configures a count threshold that must be exceeded before STAT_INT_ECC_1BIT_THRESH is asserted and STAT_ECC_ERROR_1BIT_CNT_PSx begin to count. Reset value 8'b0.
STAT_INT_ECC_1BIT_THRESH_PS0 0x05864 D[0] : This bit is set when the number of 1-bit ECC errors exceeds the threshold defined in CFG_ECC_1BIT_INT_THRESH. Reading this register automatically clears it. Reset value 1’b0
STAT_INT_ECC_1BIT_THRESH_PS1 0x05868 D[0] : This bit is set when the number of 1-bit ECC errors exceeds the threshold defined in CFG_ECC_1BIT_INT_THRESH. Reading this register automatically clears it. Reset value 1’b0.
STAT_DFI_INIT_COMPLETE 0x10034 D[0] : This value is set to ‘1’ when PHY initialization has completed. Reset value 1’b0.
STAT_DFI_CATTRIP 0x1004C D[0] : This register will be set if the temperature ever exceeds the catastrophic value per HBM2 Jedec specification. Reset value 1’b0

Address decode example:

To read the STAT_ECC_ERROR_1BIT_CNT for Memory Controller 4, Pseudo Channel 1, look for the STAT_ECC_ERROR_1BIT_CNT_PS1 register. The lower 17-bit address is 0x05834. Memory Controller 4 has an upper 5-bit address value of 5'b01010. Prepending these 5 bits yields the address 22’h145834.

Activity Monitor Control/Status Registers

Each Memory Controller contains counters for tracking usage statistics. This information may be useful for monitoring performance under varying real-time traffic conditions. Registers are 32 bits unless specified otherwise in the register definition.

The Activity Monitor can be used in one of two modes defined by INIT_AM_REPEAT_EN:

  1. Repeating interval – Usage statistics are collected over a configurable time interval and saved to registers after completion of the interval. This process then automatically repeats.
  2. Single interval – Usage statistics are collected over a configurable time interval and saved to registers after completion of the interval. This process only occurs once.

Typical repeating usage would be as follows:

  1. Configure the capture interval (CFG_AM_INTERVAL) to the desired value.
  2. Set the INIT_AM_REPEAT_EN to both configure and initiate the repeating data collection.
  3. Poll on STAT_AM_COMPLETE to know when the collection has completed and the tracking registers have updated data. Note that STAT_AM_COMPLETE is self-clearing. Thus, after a 1 is read back there is no need to reset the register for the next cycle.
  4. Read back the desired tracking registers for analysis.
  5. Return to step 3.

It is important to set the CFG_AM_INTERVAL to a value long enough such that you have enough time to detect completion and read back all of the desired tracking registers before the next cycle completes and the tracking registers are overwritten with new data.

A single interval use would be as follows:

  1. Configure the capture interval (CFG_AM_INTERVAL) to the desired value.
  2. Set the INIT_AM_REPEAT_EN to 0.
  3. Assert the INIT_AM_SINGLE_EN register to initiate the single interval data collection.
  4. Poll on STAT_AM_COMPLETE to know when the collection has completed and the tracking registers have updated data. Note that STAT_AM_COMPLETE is self clearing. Thus, after a 1 is read back there is no need to reset the register for the next cycle.
  5. Read back the desired tracking registers for analysis.
Table 3. Activity Monitor Control/Status Registers
Register Name Local Address Definition
INIT_AM_REPEAT 0x13800 D[0] Set to 1 to initiate the repeating interval data collection
INIT_AM_SINGLE_EN 0x13804 D[0] Set to 1 to initiate a single interval data collection
CFG_AM_INTERVAL 0x13808 D[31..0] Set the activity monitor interval, in memory clocks
STAT_AM_COMPLETE 0x1380c D[0] This is set to 1 when the interval has completed. This register is cleared on Auto-Precharge.
Table 4. Activity Monitor Tracking Registers
Register Name Local Address Definition
AM_WR_CMD_PS0 0x13814 Number of cmd=Write commands captured in the last monitoring interval. Note that this counts writes without Auto-Precharge, since writes with Auto-Precharge are a different command. For total Write commands, sum the two counts.
AM_WR_CMD_PS1 0x13818 Number of cmd=Write commands captured in the last monitoring interval. Note that this counts writes without Auto-Precharge, since writes with Auto-Precharge are a different command. For total Write commands, sum the two counts.
AM_WR_AP_CMD_PS0 0x13820 Number of cmd=Write-with-Auto-Precharge commands captured in the last monitoring interval.
AM_WR_AP_CMD_PS1 0x13824 Number of cmd=Write-with-Auto-Precharge commands captured in the last monitoring interval.
AM_RD_CMD_PS0 0x1382c Number of cmd=Read commands captured in the last monitoring interval. Note that this counts reads without Auto-Precharge, since reads with Auto-Precharge are a different command. For total Read commands, sum the two counts.
AM_RD_CMD_PS1 0x13830 Number of cmd=Read commands captured in the last monitoring interval. Note that this counts reads without Auto-Precharge, since reads with Auto-Precharge are a different command. For total Read commands, sum the two counts.
AM_RD_AP_CMD_PS0 0x13838 Number of Read with Auto-Precharge commands captured in the last monitoring interval.
AM_RD_AP_CMD_PS1 0x1383c Number of Read with Auto-Precharge commands captured in the last monitoring interval.
AM_REFRESH_CMD_PS0 0x13844 Number of Refresh commands captured in the last monitoring interval.
AM_REFRESH_CMD_PS1 0x13848 Number of Refresh commands captured in the last monitoring interval.
AM_ACT_CMD_PS0 0x13850 Number of Activate commands captured in the last monitoring interval.
AM_ACT_CMD_PS1 0x13854 Number of Activate commands captured in the last monitoring interval.
AM_PRECHARGE_CMD_PS0 0x1385c Number of Precharge (single-bank) commands captured in the last monitoring interval.
AM_PRECHARGE_CMD_PS1 0x13860 Number of Precharge (single-bank) commands captured in the last monitoring interval.
AM_PRECHARGE_ALL_CMD_PS0 0x13868 Number of times any Read command (Read or Read with Auto-Precharge) is followed by any Write command (Write or Write with Auto-Precharge) in the last monitoring interval.
AM_PRECHARGE_ALL_CMD_PS1 0x1386c Number of times any Read command (Read or Read with Auto-Precharge) is followed by any Write command (Write or Write with Auto-Precharge) in the last monitoring interval.
AM_POWER_DOWN 0x13870 Number of clock cycles the memory is in power-down in the last monitoring interval.
AM_SELF_REFRESH 0x13874 Number of clock cycles the memory is in self-refresh in the last monitoring interval.
AM_RD_TO_WR_SWITCH_PS0 0x1387c Number of times any Read command (Read or Read with Auto-Precharge) is followed by any Write command (Write or Write with Auto-Precharge) in the last monitoring interval.
AM_RD_TO_WR_SWITCH_PS1 0x13880 Number of times any Read command (Read or Read with Auto-Precharge) is followed by any Write command (Write or Write with Auto-Precharge) in the last monitoring interval.
AM_RO_AGE_LIMIT_PS0 0x13888 Number of times the reorder queue entry reaches its age limit in the last monitoring interval.
AM_RO_AGE_LIMIT_PS1 0x1388c Number of times the reorder queue entry reaches its age limit in the last monitoring interval.
AM_RMW_CYCLE_PS0 0x13894 Number of Read Modify Write cycles in the last monitoring interval.
AM_RMW_CYCLE_PS1 0x13898 Number of Read Modify Write cycles in the last monitoring interval.