Non-AXI Ports - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

Document ID
PG276
Release Date
2021-08-06
Version
1.0 English
A single 32-bit APB register bus with 22 bits of addressing provides access to all the documented status registers for each HBM controller stack. For naming and protocol definitions, see the AMBA AXI Protocol Specification.
Note: apb_slv_error is not used.

There is one port per stack to indicate the end of initial configuration sequence through the internal APB master. This port is apb_complete_0 for Stack-0 APB interface and apb_complete_1 for Stack-1 APB interface. You need to monitor these ports and wait until they sample high before starting any transaction on the AXI3 interface.