Product Specification - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

Document ID
PG276
Release Date
2021-08-06
Version
1.0 English

The AXI High Bandwidth Memory Controller provides user logic access to the attached HBM through the AXI3 ports distributed throughout the general interconnect. Each of the 16 AXI3 ports per stack has a throughput capacity equal to 1/16 of the total HBM bandwidth.

Each of these ports has pipeline registers to facilitate timing closure and routing of user logic. Each port can optionally address the entire HBM space (global addressing) to greatly reduce the need for any cross channel routing in general interconnect. Alternatively, non-global addressing (direct addressing) limits an AXI3 port to the associated pseudo channel with the least latency.

The eight memory controllers in a stack each have flexibility to optimize latency and utilization trade-offs for a given application by using different reordering or operating modes. Also, activity monitoring registers are provided to facilitate analysis.

Reliability is enhanced with full datapath parity checking and optional SECDED ECC protection in memory. Error logging is provided by ECC status registers.