Reliability Options Tab - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

Document ID
PG276
Release Date
2021-08-06
Version
1.0 English

The following figure shows the Reliability Options tab for the HBM IP.

Figure 1. AXI HBM Customize IP – Reliability Options Tab

Hardware Debug Options

Enable Hardware Debug Interface
Enable the XSDB hardware debugger core in the HBM IP to see the HBM properties and status in the Vivado Hardware Manager.

ECC Options

Enable ECC Bypass
When enabled, the controller will not compute ECC check data or perform ECC correction on received data. In ECC bypass mode, wdata_parity input pins are repurposed to be the data that gets written to ECC memory. Likewise, rdata_parity outputs are repurposed to be the data that gets read out of ECC memory.
Enable ECC Correction
When selected, single bit errors are corrected and double bit errors are only detected. In both cases these values are logged in status registers.
Enable ECC Scrubbing
This option requires ECC Correction to be enabled. This enables continuous scrubbing of the memory, correcting single bit errors.
ECC Scrub Bits
Number of memory address bits to use for ECC Initialization and Scrubbing. If set to 0, the default max number of bits for the currently configured memory will be used.
ECC Scrub Period
Period between read operations for ECC scrubbing. This value is in units of 256 memory clock periods. For example, a value of 2 means a delay of 2x256=512 memory controller clock periods between each read.
Initialize Memory Using ECC
This option requires ECC Correction to be enabled. This initializes the full memory array with valid ECC values.
Write Data Mask
This option is not compatible with ECC Correction. This enables the ability to use Write Data Mask.

Parity Options

Controller DQ Parity
Enables Write and Read Controller DQ parity. This is generated by HBM controller as per the JEDEC specification. Retry is also enabled when this option is selected.
AXI Interface Parity
Enable the top level AXI Write/Read data parity ports and set the expectation that the user must provide Write parity data along with the Write payload bursts. When enabled, a BRESP SLVERR will occur if the Write DQ parity is not matched with the payload. User application must check the read DQ parity data against the response payload for errors. Odd parity is calculated per 8 bits of data. So, for 256 bits of data bus there are 32 bits of parity port.
Command/Address Parity
Enables the use of the parity bits for command and address.