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AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

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Minimal CLB and block RAM resources are required to support the HBM stack controller. Primarily the logic is used for register initialization based on the values set in the Vivado® HBM wizard. Additional CLB resources are used for the clocks required for the design, the enabled AXI interface(s), and the APB register interface. The following figure shows the HBM controller initialization logic.

Figure 1. CLB-Based Initialization Logic