Simulation - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

Document ID
PG276
Release Date
2021-08-06
Version
1.0 English

When building custom simulation scripts, there are .MEM files which contain IP settings which must be included in the simulation. There is one .MEM file for each memory stack: xpm_internal_config_file_sim_0.mem and xpm_internal_config_file_sim_1.mem. By default, these are located in the project/project.srcs/sources_1/ip/hbm_0/hdl/rtl directory. Not including these files will likely result in calibration failure in simulation. These files are automatically included if launching simulation runs within the Vivado environment.

HBM IP simulation is only supported with Verilog Compiler Simulator (VCS), Incisive Enterprise Simulator (IES), and Mentor Graphics Questa Advanced Simulator. Simulation is not supported natively with the Vivado Simulator.

For comprehensive information about Vivado® simulation components, as well as information about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900).