The simulation log files, stimulus generator file, and results can be found in the following directory: Example_design_directory/ip_top_name_ex/ip_top_name_ex.sim/sim_1/behav/vcs
The main simulation log file is simulate.log. This file has the transcript from the memory model. Also, towards the end of the log file the performance numbers for each master are listed. The following is an example:
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>>>>>> SRC_ID 1 :: AXI_PMON :: BW ANALYSIS >>>>>>
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AXI Clock Period = 2000 ps
Min Write Latency = 30 axi clock cycles
Max Write Latency = 180 axi clock cycles
Avg Write Latency = 163 axi clock cycles
Actual Achieved Write Bandwidth = 15724.815725 Mb/s
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Min Read Latency = 263 axi clock cycles
Max Read Latency = 2228 axi clock cycles
Avg Read Latency = 1369 axi clock cycles
Actual Achieved Read Bandwidth = 4894.837476 Mb/s
To change the default stimulus, the axi_tg.txt file needs to be updated. For more details about the stimulus file, see the Non-Synthesizable Traffic Generator section.
The stimulus file, axi_tg.txt, holds the description of the behavior of all the masters that need to be simulated. The CSV files from all masters need to be concatenated in this file. Refer to axi_tg.txt generated in the example design project.