Test Bench - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

Document ID
PG276
Release Date
2021-08-06
Version
1.0 English

Only one traffic generator is supplied in the example design for PHY only mode. This traffic generator is used for both the synthesis/implementation and simulation flows. Consequently, the option Example TG for Simulation is grayed out and the only available option is SYNTHESIZABLE.

The test bench for PHY only mode performs Write and Read operations. In simulation mode, after performing a few Write and Read operations, the simulation stops and performs a data integrity check. While running on hardware, continuous Write and Read transaction traffic is sent and data integrity checking is also performed in parallel.