When the “Add VIO” option is selected in the Example Design Options tab of the IP configuration
GUI a set of VIOs will be instantiated for every traffic generator enabled in the
design. These can be seen in the VIO dashboard in the Vivado
Hardware Manager when the design is running on hardware. For these configurations the
vio_tg_start_x signal must be set to 1’b1 to start each traffic
generator in the design. To pause the traffic generator set the
vio_tg_pause_x signal to 1’b1. To resume traffic set
vio_tg_pause_x to 1’b0 while vio_tg_start_x is
still 1’b1. If a data error was detected then the compare error status is latched to the
axi_x_data_msmatch_err signal. This signal will remain asserted
until the entire design is reset. During operation the wr_cnt_x and
rd_cnt_x will increment for every Write or Read transaction. These counters
will not reset unless the entire design is reset.