WRITE - 1.0 English

AXI High Bandwidth Memory Controller v1.0 LogiCORE IP Product Guide (PG276)

Document ID
PG276
Release Date
2021-08-06
Version
1.0 English

Issues a Write command. The following table describes the WRITE command input fields and options:

Table 1. WRITE Command Input Fields and Options
Command Input Field Options
txn_count
  • <value in dec> – Repeat the current command n times.
  • <value in dec>KB – Amount of data to be transferred in KB. For example, 50 KB, 100 KB, etc.
  • <value in dec>MB – Amount of data to be transferred in MB. For example, 5 MB, 10 MB, etc.
  • <value in dec>GB – Amount of data to be transferred in GB. For example, 1 GB, 2 GB, etc.
start_delay
  • <value in number of clks (dec) > – Issue transaction after specified number of clks.
  • <bandwidth in dec > Mb/s – Bandwidth for Write transactions. For example, 12,500 Mb/s.
inter_beat_delay
  • <value in number of clks (dec) >
  • Add specified delay between two beats in an AXI transaction.
wdata_pattern
  • random – Random data is generated on all Write data beats. wdata_pat_value field gives a seed value for RNG.
  • same_as_src – All Write data beats are generated with PARAM_SRC_ID value.
  • same_as_addr – All Write data beats are generated with the corresponding beat start address.
  • constant – All Write data beats are generated with the constant value is set on wdata_pat_value field.
  • walking_1 – The value of 1 walks through (bit wise) the Write data beats where rest of bits are 0
  • walking_0 – The value of 0 walks through (bit wise) the Write data beats where rest of bits are 1.
wdata_pat_value
  • <seed_value in hex> – When wdata_pattern is selected as random, this field value is used as the seed for the RNG.
  • <value in hex> – When wdata_pattern is selected as constant, this value is used as constant data which sent in all Write data beats.
data_integrity
  • enabled – Data integrity checks are enabled for the Write transaction. For example, the transaction data is stored in the memory by AXI-TG to compare later when Read occurs to this location.
  • disabled – Data integrity checks are disabled for this Write transaction. For example, Read data comparison is not available.
addr_incr_by
  • <value in hex> – This field is used when axi_addr is set to start_addr value. If txn_count > 0, for each AXI transaction issued, increment the address by the specified value. If add_incr_by = 0, all transactions are issues with same axi_addr.
  • <seed_value in hex> – This field value is used as the seed for RNG to generate random addr when axi_addr field is set any one of the following options: random, random_aligned, random_unaligned, random_uniform, random_uniform_aligned, or random_uniform_unaligned.
  • auto_incr – The first transactions start address is picked from axi_addr field and then each transactions start addresses are calculated by using this expression: start_address (from second txn) = previous_start_address + ((1<<axi_size) × (axi_len+1)).
  • For example, txn_count 3, axi_addr 0000_0000, axi_size 6, axi_len 0. The start address of all three transactions are: First txn start address: 0000_0000, Second txn start address: 0000_0000 + ((1<<6) × (0+1)) = 0000_0040, Third txn start address: 0000_0040 + ((1<<6) × (0+1)) = 0000_0080
dest_id
  • <value in hex> – Targeted slave ID value can be given in this field for the transaction.
  • <Parameters> – Targeted slave ID can be given using Parameters such SLAVE_DST_ID0, SLAVE_DST_ID1, These parameters hold the slave ID value in adv_axi_tg top.
base_addr
  • <value in hex>
  • The base_addr can be specified in this field. The incremented addr for the txns are looped back to the base address when the high address boundary is reached.
high_addr
  • The high address can be specified here. The traffic generator increments up to this value. After the incremented addr reaches the high_addr boundary, the next transaction start address is the base_addr.
axi_addr
  • <value in hex> – AXI transaction start address value. If txn_count > 0, the next transaction address is calculated using addr_incr_by.
  • random – Any random address is generated between base_addr and high_addr. addr_incr_by field value is set as the seed to the RNG.
  • random_aligned – Any random aligned address is generated between base_addr and high_addr. addr_incr_by field value is set as the seed to the RNG.
  • random_unaligned – Any random unaligned address is generated between base_addr and high_addr. addr_incr_by field value is set as the seed to the RNG.
  • random_uniform – Uniformly distributed random addr is generated between base_addr and high_addr. addr_incr_by field value is set as the seed to the RNG.
  • random_uniform_aligned – Uniformly distributed random aligned addr is generated between base_addr and high_addr. addr_incr_by field value is set a the seed to the RNG.
  • random_uniform_unaligned – Uniformly distributed random unaligned addr is generated between base_addr and high_addr. addr_incr_by field value is set as the seed to the RNG.
axi_len
  • This hex value passes to the AXI_xx_AWLEN port.
axi_size
  • This hex value passes to the AXI_xx_AWSIZE port.
axi_id
  • <value in hex> – All the Write transactions are sent with this ID.
  • auto_incr – The first Write transaction is sent out with ID of 0 and the each consecutive transactions IDs is incremented by 1.
axi_burst
  • <value in hex> – 0x1, 0x2
  • INCR, WRAP
axi_lock
  • Set to 0, this AXI port is not used in the HBM IP.
axi_cache
  • Set to 0, this AXI port is not used in the HBM IP.
axi_prot
  • Set to 0, this AXI port is not used in the HBM IP.
axi_qos
  • Set to 0, this AXI port is not used in the HBM IP.
axi_region
  • Set to 0, this AXI port is not used in the HBM IP.
axi_user
  • Set to 0, thi s AXI port is not used in the HBM IP.

The following table shows the reset values for the WRITE command.

Table 2. Reset Values for the Write Command
Command Input Field WRITE (Reset Value)
txn_count 100
start_delay 0
inter_beat_delay 0
wdata_pattern Constant
wdata_pat_value 0
data_integrity Disabled
dest_id SLAVE_DST_ID0 (TG Parameter)
base_addr

C_AXI_WR_BASEADDR

(TG Parameter)

high_addr

C_AXI_WR_HIGHADDR

(TG Parameter)

addr_incr_by auto_incr
axi_addr 0
axi_len 0
axi_size

C_AXI_WRITE_MAX_SIZE

(TG Parameter)

axi_id auto_incr
axi_burst 1
axi_lock 0
axi_cache 2
axi_prot 0
axi_qos 0
axi_region 0
axi_user 0