The following table summarizes the signals, which are either shared by, or not part of the dedicated AXI4-Stream, memory mapped AXI4 data, or AXI4-Lite control interfaces.
|ap_clk||I||1||Video core clock|
|ap_rst_n||I||1||Video core active-Low clock enable|
|interrupt||O||1||Interrupt Request Pin|
|field_id||O (Frame Buffer Read)||1||Field polarity (only available when interlaced support is selected)|
|I (Frame Buffer Write)|
ap_rst_n signals are shared between
the core, the AXI4-Stream, memory mapped AXI4 data interface, and the AXI4-Lite