Example Design - 2.5 English

Video Frame Buffer Read and Video Frame Buffer Write LogiCORE IP Product Guide (PG278)

Document ID
PG278
Release Date
2023-10-19
Version
2.5 English
This chapter provides two example systems: one containing the Video Frame Buffer Read and the other one containing both the Video Frame Buffer Read and the Video Frame Buffer Write cores. Important system-level aspects when designing with the cores are highlighted in the example designs, including:
  • Typical usage of the Video Frame Buffer Read and Video Frame Buffer Write in conjunction with other cores.
  • Runtime configuration of the Video Frame Buffer Read and Video Frame Buffer Write by programming registers on-the-fly.

The supported platforms are listed in the following table.

Table 1. Supported Platforms
Development Boards Additional Hardware Processor
KC705 N/A MicroBlaze™
ZCU102 N/A psu_cortexa53_0
ZCU104 N/A psu_cortexa53_0
ZCU106 N/A psu_cortexa53_0
VCK190 N/A CIPS

To open the example project, perform the following:

  1. Select the Video Frame Buffer Read IP or Video Frame Buffer Write IP from the AMD Vivado™ IP catalog.
  2. Double-click the selected IP or right-click the IP and select Customize IP from the menu.
  3. Configure the parameters in the Customize IP window as needed and click OK.
  4. In the Generate Output Products window, select Generate or Skip. If Generate is selected, the IP output products are generated after a brief moment.
  5. Right-click Video Frame Buffer Read or Video Frame Buffer Write in the Sources panel and select Open IP Example Design from the menu.
  6. In the Open IP Example Design window, select the example project directory and click OK. The Vivado software then runs automation to generate the example design in the selected directory.