Memory Mapped AXI4 Interface - 2.5 English

Video Frame Buffer Read and Video Frame Buffer Write LogiCORE IP Product Guide (PG278)
Document ID
PG278
Release Date
2023-10-19
Version
2.5 English

The memory mapped AXI4 interface runs on the ap_clk clock domain. The signals follow the specification as defined in the Vivado Design Suite: AXI Reference Guide (UG1037). The Video Frame Buffer Read and Video Frame Buffer Write support the pixel formats in memory described in the following table.

Table 1. Pixel Formats
Video Format ID Description Bits per Component Bytes per Pixel
RGBX8 10 packed RGB 8 4 bytes per pixel
BGRX8 27 packed BGR 8 4 bytes per pixel
YUVX8 11 packed YUV 4:4:4 8 4 bytes per pixel
YUYV8 12 packed YUV 4:2:2 8 2 bytes per pixel
UYVY8 28 packed YUV 4:2:2 8 2 bytes per pixel
RGBA8 1 13 packed RGB with alpha 8 4 bytes per pixel
BGRA8 1 26 packed BGR with alpha 8 4 bytes per pixel
YUVA8 1 14 packed YUV 4:4:4 with alpha 8 4 bytes per pixel
RGBX10 15 packed RGB 10 4 bytes per pixel
YUVX10 16 packed YUV 4:4:4 10 4 bytes per pixel
Y_UV8 18 semi-planar YUV 4:2:2 8 1 byte per pixel per plane
Y_UV8_420 19 semi-planar YUV 4:2:0 8 1 byte per pixel per plane
RGB8 20 packed RGB 8 3 bytes per pixel
BGR8 29 packed BGR 8 3 bytes per pixel
YUV8 21 packed YUV 4:4:4 8 3 bytes per pixel
Y_UV10 22 semi-planar YUV 4:2:2 10 4 bytes per 3 pixels per plane
Y_UV10_420 23 semi-planar YUV 4:2:0 10 4 bytes per 3 pixels per plane
Y8 24 packed luma only 8 1 byte per pixel
XY10 25 packed luma only 10 4 bytes per 3 pixels
RGBX12 30 packed RGB 12 5 bytes per pixel
YUVX12 31 packed YUV 4:4:4 12 5 bytes per pixel
Y_UV12 32 semi-planar YUV 4:2:2 12 3 bytes per 2 pixels
Y_UV12_420 33 semi-planar YUV 4:2:0 12 3 bytes per 2 pixels
Y12 34 packed luma only 12 3 bytes per 2 pixels
RGB16 35 packed RGB 16 6 bytes per pixel
YUV16 36 packed YUV 4:4:4 16 6 bytes per pixel
Y_UV16 37 semi-planar YUV 4:2:2 16 2 bytes per pixel
Y_UV16_420 38 semi-planar YUV 4:2:0 16 2 bytes per pixel
Y16 39 packed luma only 16 2 bytes per pixel
Y_U_V8 42 3 planar YUV 4:4:4 8 1 byte per pixel
Y_U_V8_420 41 3 PLANAR YUV 4:2:0 8 1 byte per pixel
Y_U_V10 43 3 planar YUV 4:4:4 10 4 byte per pixel
  1. Per pixel alpha memory formats are only available with Video Frame Buffer Read IP.

The following table shows the IP format with the corresponding V4L2 and DRM pixel formats.

Table 2. IP Format to Common Video Pixel Format
IP Format V4L2 4CC DRM 4CC
RGBX8 V4L2_PIX_FMT_BGRX32 DRM_FORMAT_XBGR8888
BGRX8 V4L2_PIX_FMT_XRGB32 DRM_FORMAT_XRGB8888
YUVX8 V4L2_PIX_FMT_XVUY32 DRM_FORMAT_XVUY8888
YUYV8 V4L2_PIX_FMT_YUYV DRM_FORMAT_YUYV
UYVY8 V4L2_PIX_FMT_UYVY DRM_FORMAT_UYVY
RGBA8 Not supported Not supported
BGRA8 Not supported Not supported
YUVA8 Not supported Not supported
RGBX10 V4L2_PIX_FMT_XBGR30 DRM_FORMAT_XBGR2101010
YUVX10 V4L2_PIX_FMT_XVUY10 DRM_FORMAT_XVUY2101010
Y_UV8 V4L2_PIX_FMT_NV16 DRM_FORMAT_NV16
Y_UV8_420 V4L2_PIX_FMT_NV12 DRM_FORMAT_NV12
RGB8 V4L2_PIX_FMT_RGB24 DRM_FORMAT_BGR888
BGR8 V4L2_PIX_FMT_BGR24 DRM_FORMAT_RGB888
YUV8 V4L2_PIX_FMT_VUY24 DRM_FORMAT_VUY888
Y_UV10 V4L2_PIX_FMT_XV20M DRM_FORMAT_XV20
Y_UV10_420 V4L2_PIX_FMT_XV15M DRM_FORMAT_XV15
Y8 V4L2_PIX_FMT_GREY DRM_FORMAT_Y8
XY10 V4L2_PIX_FMT_XY10 1 DRM_FORMAT_Y10
RGBX12 V4L2_PIX_FMT_XBGR40 1 Not supported
YUVX12 Not supported Not supported
Y_UV12

V4L2_PIX_FMT_X212 1

V4L2_PIX_FMT_X212M 1

Not supported
Y_UV12_420

V4L2_PIX_FMT_X012 1

V4L2_PIX_FMT_X012M 1

Not supported
Y12 V4L2_PIX_FMT_XY12 1 Not supported
RGB16 V4L2_PIX_FMT_BGR48 Not supported
YUV16 Not Supported Not supported
Y_UV16

V4L2_PIX_FMT_X216 1

V4L2_PIX_FMT_X216M 1

Not supported
Y_UV16_420

V4L2_PIX_FMT_X016 1

V4L2_PIX_FMT_X016M 1

Not supported
Y16 V4L2_PIX_FMT_Y16 Not supported
  1. AMD only formats M – Noncontiguous planes (Chroma plane does not start at the end of Luma plane).

The following tables explain the expected pixel mappings in memory for each of the mentioned listed formats.

Note: RGB formats are stored in memory in RGB order, which is different from the pixel mapping in AXI4-Stream Video IP and System Design Guide (UG934).