The Video Frame Buffer read and write IPs must be configured for the actual input and output image frame size to operate properly. The IP can be connected to the Video In to AXI4-Stream input and the Video Timing Controller core to gather the frame size information from the image video stream. The timing detector logic in the Video Timing Controller gathers the video timing signals. The AXI4-Lite control interface on the Video Timing Controller allows the system processor to read out the measured frame dimensions and program all downstream cores, such as the Video Frame Buffer Read and Video Frame Buffer Write, with the appropriate image dimensions.
Ensure that there is sufficient bandwidth available to the Video Frame Buffer Read and Video Frame Buffer Write. The bandwidth required (in MB/s) can be calculated with the following equation:
where fps is the number of frames per second
the Video Frame Buffer Read and Video Frame Buffer Writeis operating at;
height is the height in lines;
stride is the stride value in bytes. See
Stride in Prerequisites for more
information on stride.