AXI4-Lite Interface - 1.2 English

Gamma Look Up Table LogiCORE IP Product Guide (PG285)
Document ID
PG285
Release Date
2023-05-17
Version
1.2 English

The AXI4-Lite interface allows you to dynamically control parameters within the core. Core configuration can be accomplished using an AXI4-Lite master state machine, or an embedded Arm or soft system processor such as a MicroBlaze ™ processor.

The Gamma LUT core can be controlled through the AXI4-Lite interface by using functions provided by the driver in the AMD Vitis ™ software platform. Another method is performing read and write transactions to the Gamma LUT register space; this method should only be used when the first method is not available.

Table 2-3: AXI4-Lite Interface Signals

Signal Name

Direction

Width

Description

s_axi_CTRL_awvalid

I

1

AXI4-Lite Write Address Channel Write Address Valid.

s_axi_CTRL_awread

O

1

AXI4-Lite Write Address Channel Write Address Ready. Indicates DMA ready to accept the write address.

s_axi_CTRL_awaddr

I

32

AXI4-Lite Write Address Bus

s_axi_CTRL_wvalid

I

1

AXI4-Lite Write Data Channel Write Data Valid.

s_axi_CTRL_wready

O

1

AXI4-Lite Write Data Channel Write Data Ready. Indicates DMA is ready to accept the write data.

s_axi_CTRL_wdata

I

32

AXI4-Lite Write Data Bus

s_axi_CTRL_bresp

O

2

AXI4-Lite Write Response Channel. Indicates results of the write transfer.

s_axi_CTRL_bvalid

O

1

AXI4-Lite Write Response Channel Response Valid. Indicates response is valid.

s_axi_CTRL_bready

I

1

AXI4-Lite Write Response Channel Ready. Indicates target is ready to receive response.

s_axi_CTRL_arvalid

I

1

AXI4-Lite Read Address Channel Read Address Valid

s_axi_CTRL_arready

O

1

Ready. Indicates DMA is ready to accept the read address.

s_axi_CTRL_araddr

I

32

AXI4-Lite Read Address Bus

s_axi_CTRL_rvalid

O

1

AXI4-Lite Read Data Channel Read Data Valid

s_axi_CTRL_rready

I

1

AXI4-Lite Read Data Channel Read Data Ready. Indicates target is ready to accept the read data.

s_axi_CTRL_rdata

O

32

AXI4-Lite Read Data Bus

s_axi_CTRL_rresp

O

2

AXI4-Lite Read Response Channel Response. Indicates results of the read transfer.