This chapter describes customizing and generating the core, constraining the core, and the simulation, synthesis and implementation steps that are specific to this IP core. More detailed information about the standard AMD Vivado™ design flows and the IP integrator can be found in the following AMD Vivado™ Design Suite user guides:
• (UG994) [Ref 9]
• (UG896) [Ref 5]
• (UG910) [Ref 7]
• (UG900) [Ref 8]