• Programmable gamma table supports gamma correction or any user defined function
• Three channel independent look-up table structure
• One, two, four or eight pixel-wide AXI4-Stream video interface
• 8 and 10 bits per component support
• Supports spatial resolutions from 64 x 64 up to 8192 x 4320
• Supports 8K60 in all supported device families (performance on low power devices might be lower)
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LogiCORE IP Facts Table |
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|---|---|---|---|---|---|
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Core Specifics |
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AMD Versal ™ Adaptive SoC, AMD UltraScale+ ™ Families, AMD UltraScale™ Architecture, AMD Zynq ™ 7000 , AMD 7 Series |
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Supported User Interfaces |
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Provided with Core |
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Documentation |
Product Guide |
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Design Files |
Not Provided |
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Example Design |
Yes |
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Test Bench |
Not Provided |
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Constraints File |
XDC |
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Simulation Models |
Encrypted RTL, VHDL or Verilog Structural |
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Standalone, V4L2 |
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Design Entry Tools |
AMD Vivado ™ Design Suite |
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Simulation |
For supported simulators, see Vivado Design Suite User Guide: Release Notes, Installation, and Licensing. |
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Synthesis Tools |
Vivado Synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 68768 |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes: 1. For a complete listing of supported devices, see the Vivado IP Catalog. 2. Video protocol as defined in the section of [Ref 1] . 3. Standalone driver details can be found in the Vitis directory (<install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm). Linux OS and driver support information is available from the Linux Gamma LUT Driver page . 4. For the supported versions of the tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing. |
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