Register Space - 1.2 English

Gamma Look Up Table LogiCORE IP Product Guide (PG285)

Document ID
PG285
Release Date
2023-05-17
Version
1.2 English

The core has seven core-specific registers which allow you to dynamically control the operation of the core. All registers have an initial value of 0. Table: Register Names and Descriptions describes the register names.

Table 2-4: Register Names and Descriptions

Address (hex) BASEADDR +

Register Name

Access Type

Register Description

0x0000

Control

R/W

Bit 0: ap_start (R/W/COH) (1)

Bit 1: ap_done (R/COR) (1)

Bit 2: ap_idle (R)

Bit 3: ap_ready (R)

Bit 7: auto_restart (R/W)

Others: reserved

0x0004

Global Interrupt Enable

R/W

Bit 0: Global Interrupt Enable

Others: reserved

This register is not used but reserved for future use.

0x0008

IP Interrupt Enable Register

R/W

Bit 0: Channel 0 (ap_done)

Bit 1: Channel 1 (ap_ready)

Others: reserved

This register is not used but reserved for future use.

0x000C

IP Interrupt Status Register

R

Bit 0: Channel 0 (ap_done)

Bit 1: Channel 1 (ap_ready)

Others: reserved

This register is not used but reserved for future use.

0x0010

Active Width

R/W

Number of Active Pixels per Scanline

0x0018

Active Height

R/W

Number of Active Lines per Frame

0x0020

Video Format

R/W

Specify AXI4 Stream video color format

0x0800

Gamma look-up table 0 (RED)

R/W

Word n: bit [15:0] Gamma LUT 0 [2n]

bit [31:16] Gamma LUT 0 [2n+1]

0x1000

Gamma look-up table 1 (GREEN)

R/W

Word n: bit [15:0] Gamma LUT 1 [2n]

bit [31:16] Gamma LUT 1 [2n+1]

0x1800

Gamma look-up table 2 (BLUE)

R/W

Word n: bit [15:0] Gamma LUT 2 [2n]

bit [31:16] Gamma LUT 2 [2n+1]

Notes:

1. COR = Clear on Read, COH - Clear on Handshake

2. Control Register (0x0000), Global Interrupt Enable Register (0x0004), IP Interrupt Enable Register (0x0008), and IP Interrupt Status Register (0x000C) are explained in section ‘S_AXILITE Control Register Map’ of Vitis High-Level Synthesis User Guide (UG1399) [Ref 10] . In UG1399, these registers definitions may have some additional bits; however, in this IP, bits mentioned in Table: Register Names and Descriptions . Therefore, only these bits need to be considered while accessing the Control Register, Global Interrupt Enable Register, IP Interrupt Enable Register, and IP Interrupt Status Register.