Detailed Example Design - 1.1 English

Sensor Demosaic LogiCORE IP Product Guide (PG286)

Document ID
PG286
Release Date
2023-05-16
Version
1.1 English

This chapter provides two example systems that include the Sensor Demosaic core, a simulation example design and a synthesizable example design. The example designs highlight the following key system-level aspects of designing with the Sensor Demosaic core:

  • Typical usage of sensor demosaic with other cores and AXI master.
  • Configuration of sensor demosaic registers on the fly.

The supported platforms are listed in the following table.

Table 1. Supported Platforms
Development Boards Additional Hardware Processor
KC705 N/A MicroBlaze™ processor
ZCU102 N/A A53
ZCU104 N/A A53
ZCU106 N/A A53
VCK190 N/A CIPS

To open the example project, perform the following steps:

  1. Select the Sensor Demosaic IP from IP Catalog.
  2. Double-click on the selected IP or right-click the IP and select Customize IP from the menu.
  3. Configure the build-time parameters in the Customize IP window and click OK. The AMD Vivado™ IDE generates an example design matching the build-time configuration.
  4. In the Generate Output Products window, select Generate or Skip. If Generate is selected, the output products of the IP are generated after a brief moment.
  5. Right-click Sensor Demosaic in Sources panel and select Open IP Example Design from the menu.
  6. In the Open IP Example Design window, select example project directory and click OK. The Vivado software then runs automation to generate example design in selected directory.

The generated project contains two example designs. The following figure shows the Source panel of the example project. The synthesizable example block design, along with the top-level file, resides in the Design Sources catalog. Simulation example design files (including the block design file, SystemVerilog test bench, and another task file) are under Simulation Sources.

Figure 1. Example Project Source Panel