Register Space - 1.1 English

Sensor Demosaic LogiCORE IP Product Guide (PG286)

Document ID
PG286
Release Date
2022-05-11
Version
1.1 English

The core has seven core-specific registers which allow you to dynamically control the operation of the core. All registers have an initial value of 0. Table: Register Names and Descriptions describes the register names.

Table 2-6: Register Names and Descriptions

Address (hex) BASEADDR +

Register Name

Access Type

Register Description

0x0000

Control

R/W

Bit 0: ap_start (R/W/COH) (1)

Bit 1: ap_done (R/COR) (1)

Bit 2: ap_idle (R)

Bit 3: ap_ready (R)

Bit 7: auto_restart (R/W)

Others: reserved

0x0004

Global Interrupt Enable

R/W

Bit 0: Global Interrupt Enable

Others: reserved

This register is not used but reserved for future use.

0x0008

IP Interrupt Enable Register

R/W

Bit 0: ap_done

Bit 1: ap_ready

Others: reserved

This register is not used but reserved for future use.

0x000C

IP Interrupt Status Register

R/TOW (1)

Bit 0: ap_done

Bit 1: ap_ready

Others: reserved

This register is not used but reserved for future use.

0x0010

Active Width

R/W

Number of Active Pixels per Scanline

0x0018

Active Height

R/W

Number of Active Lines per Frame

0x0028

Bayer Phase

R/W

Bits 1-0: Bayer sampling grid starting position

Notes:

1. COR = Clear on Read, COH - Clear on Handshake, TOW- Toggle on Write

2. Control Register (0x0000), Global Interrupt Enable Register (0x0004), IP Interrupt Enable Register (0x0008), and IP Interrupt Status Register (0x000C) are explained in S_AXILITE Control Register Map of UG1399 [Ref 9] . In UG1399, these registers definitions may have some additional bits; however, in this IP, we are accessing only bits mentioned in Table: Register Names and Descriptions . Therefore, only these bits need to be considered while accessing the Control Register, Global Interrupt Enable Register, IP Interrupt Enable Register, and IP Interrupt Status Register.