Synthesizable Example Design - 1.1 English

Sensor Demosaic LogiCORE IP Product Guide (PG286)

Document ID
PG286
Release Date
2022-05-11
Version
1.1 English
Figure 5-2: Synthesizable Example Block Design

X-Ref Target - Figure 5-2

demosaic_exdes_synth.PNG

The difference between the synthesizable design and the simulation example design is the use of a processor instead of the AXI VIP core as AXI master. The locked port of AXI4-Stream to Video Out is connected to the axi_gpio_lock core and the processor polls the corresponding register for a sign that the test passed.

The synthesizable example design requires both Vivado ® and the Vitis software platform.

The first step is to run synthesis, implementation, and bitstream generation in Vivado. After all those steps are done, select File > Export > Export Hardware . In the window, select Include bitstream , select an export directory and click OK .

The remaining work is performed in the Vitis software platform. The Sensor Demosaic example design file can be found at Vitis software platform directory:

( <install_directory> / <release> /data/embeddedsw/XilinxProcessorIPLib/drivers/v_demosaic_v2_0/examples/

Example application design source files (contained within the examples folder) are tightly coupled with the Sensor Demosaic example design available in Vivado Catalog.

The vdemosaic_example.tcl file automates the process of generating the downloadable bit and . elf files from the provided example . hdf file.

To run the provided Tcl script:

1. Copy the exported example design hdf file in the examples directory of the driver.

2. Launch the Xilinx Software Command-Line Tool ( xsct ) terminal.

3. Use cd to access the examples directory.

4. Source the . tcl file:

xsct%>source vdemosaic_example.tcl

5. Execute the script:

xsct%>vdemosaic_example <xsa_file_name.xsa>

The Tcl script performs the following actions:

Creates the workspace

Creates the HW project

Creates BSP

Creates application project

Builds BSP and application project

After the process is complete, the required files are available in:

bit file -> vdemosaic_example_hw_platform/hw folder

elf file -> vdemosaic_example.sdk/vtpg_example_design/{Debug/Release} folder

Next, perform the following steps to run the software application:

IMPORTANT: To do so, make sure that the hardware is powered on and a Digilent Cable or an USB Platform Cable is connected to the host PC. Also, ensure that a USB cable is connected to the UART port of the board.

1. Launch the Vitis software platform.

2. Set the workspace to the vdemosaic_example.sdk folder in the prompted window. The Vitis software platform project opens automatically. If a welcome page shows up, close that page.

3. Download the bitstream into the FPGA by selecting Xilinx Tools > Program FPGA . The Program FPGA dialog box opens.

4. Ensure that the Bitstream field shows the bitstream file generated by the Tcl script, and then click Program .

Note: The DONE LED on the board turns green if the programming is successful.

5. A terminal program (HyperTerminal or PuTTY) is needed for UART communication. Open the program, choose the appropriate port, set the baud rate to 115200, and establish a serial port connection.

6. Select and right-click the vdemosaic_example_design application in the Project_Explorer panel.

7. Select Run As > Launch on Hardware (System Debugger).

8. Select the Binaries and Qualifier in the window, and click OK . The example design test results are shown in the terminal program.

For more information, visit www.xilinx.com/tools/vitis.htm .

When executed on the board, the example application performs the following actions:

Programs the Video Clock Generator to 1080p@60Hz

Programs the TPG and Sensor Demosaic to 1080p@60Hz

Checks for Video Lock and reports the status (PASS/FAIL) on UART

Repeats steps 1-3 for 4KP@30Hz and 4KP@60Hz