Video Data - 1.1 English

The AXI4-Stream interface specification restricts TDATA widths to integer multiples of 8 bits. Therefore, any bit data must be padded with zeros on the MSB to form a N*8 bit wide vector before connecting to s_axis_video_tdata . Padding does not affect the size of the core.

Similarly, data on the Sensor Demosaic output m_axis_video_tdata is packed and padded to multiples of 8 bits as necessary. Zero padding the most significant bits is only necessary for 10 and 12 bit wide data. Table: Dual Pixels per Clock, 10 Bits per Component Mapping for RGB and Table: Dual Pixels per Clock, 10 bits per Component Mapping for Bayer Sensor explain the pixel mapping of AXI4-Stream interface with two pixels per clock and 10 bits per component configuration.