Video Data - 1.1 English

Sensor Demosaic LogiCORE IP Product Guide (PG286)

Document ID
PG286
Release Date
2023-05-16
Version
1.1 English

The AXI4-Stream interface specification restricts TDATA widths to integer multiples of 8 bits. Therefore, any bit data must be padded with zeros on the MSB to form a N*8 bit wide vector before connecting to s_axis_video_tdata. Padding does not affect the size of the core.

Similarly, data on the Sensor Demosaic output m_axis_video_tdata is packed and padded to multiples of 8 bits as necessary. Zero padding the most significant bits is only necessary for 10 and 12 bit wide data. The following tables explain the pixel mapping of AXI4-Stream interface with two pixels per clock and 10 bits per component configuration.

Table 1. Dual Pixels per Clock, 10 Bits per Component Mapping for RGB
63:60 59:50 49:40 39:30 29:20 19:10 9:0
zero padding R1 B1 G1 R0 B0 G0
Table 2. Dual Pixels per Clock, 10 bits per Component Mapping for Bayer Sensor
23:20 19:10 9:0
Zero Padding Bayer Sample 1 Bayer Sample 0