Debug Ports - 2.0 English

PG289 SMPTE UHD-SDI TX Subsystem

Document ID
PG289
Release Date
2022-05-18
Version
2.0 English

These settings select the port to allow debugging of the core.

ERROR_O : Enables/disables the ERROR_O port.

The ERROR output has an average value of around 0. This indicates that the DPLL has converged and is locked and the PICXO phase detector has nominally the same phase and frequency on its inputs.

° Enable (fixed)

VOLT_O : Enables/disables VOLT_O port.

The VOLT output has a value that represents the difference in frequency between the local crystal oscillator (XO) and the PICXO frequency-locked output. The greater the value from 0, the further in frequency the PICXO is tracking.

° Enable (fixed)

Clock Enables : Enables/disables the clock enable ports.

° Enable (fixed)

Overflows : Enables/disables the OVF_PD port which determines overflow in the phase detector.

° Enable (fixed)

o DRPDATA_SHORT_O : Enables/disables the DRPDATA_SHORT port. DRPDATA_SHORT is not in use.

° Disable (fixed)