The example design uses the UHD-SDI GT (uhdsdi_gt_v2_0) core to configure the Xilinx® UltraScale+™ GTH transceivers and provides the option to select the transceiver reference clock. This core also generates control modules that are required to program the transceiver using the DRP interface. This Figure shows the Vivado® IDE configuration screen that is used in the ZCU106 application example design. See the UHD-SDI GT LogiCORE IP Product Guide (PG380) [Ref 15] for information on this core.
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X-Ref Target - Figure 5-3 
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