Features - 2.0 English

PG289 SMPTE UHD-SDI TX Subsystem

Document ID
PG289
Release Date
2022-05-18
Version
2.0 English

Supports AXI4-Stream, native video and native SDI user interfaces

Support for 2 pixels per sample

10-bit and 12-bit per color component

Supports YCbCr 4:4:4, YCbCr 4:2:2, and YCbCr 4:2:0 color space

Provision to insert ancillary data

Supports HLG HDR video

SMPTE 2081-10 HFR support in native SDI mode.

SMPTE 2081-10 HFR support in AXI configurations for SDI TX subsystem: supports 6G and 12G 10-bit SDI mode.

Supports block automation for Versal® ACAP device family

AXI4-Lite interface for register access to configure different subsystem options

SMPTE ST 352: Insertion of payload packets into Y Stream and C Stream are supported.

Standards compliance:

° SMPTE ST 259: SD-SDI at 270 Mb/s

° SMPTE ST 292: HD-SDI at 1.485 Gb/s and 1.485/1.001 Gb/s

° SMPTE ST 372: Dual Link HD-SDI

° SMPTE ST 424: 3G-SDI with data mapped by any ST 425-x mapping at 2.97 Gb/s and 2.97/1.001 Gb/s

° SMPTE ST 2081-1: 6G-SDI with data mapped by any ST 2081-x mapping at 5.94 Gb/s and 5.94/1.001 Gb/s

° SMPTE ST 2082-1: 12G-SDI with data mapped by any ST 2082-x mapping at 11.88 Gb/s and 11.88/1.001 Gb/s

° Dual link and quad link 6G-SDI and 12G-SDI are supported by instantiating two or four UHD-SDI transmitter subsystems.

LogiCORE IP Facts Table

Subsystem Specifics

Supported Device Family (1)

UltraScale+™ (GTHE4, GTYE4)

Versal® ACAP (GTYE5, GTYP)

Zynq® UltraScale+ MPSoC (GTHE4, GTYE4)

Zynq UltraScale+ RFSoC

Supported User Interfaces

AXI4-Lite, AXI4-Stream,

Native Video, Native SDI

Resources

Performance and Resource Utilization web page

Provided with Subsystem

Design Files

Hierarchical subsystem packaged with UHD-SDI TX IP core and other IP cores

Example Design

Vivado® IP integrator

Test Bench

N/A

Constraints File

IP cores delivered with XDC files

Simulation Model

N/A

Supported
S/W Driver
(2)

Standalone and Linux

Tested Design Flows (2)

Design Entry

Vivado® Design Suite

Simulation

Not Supported

Synthesis

Vivado Synthesis

Support

Release Notes and Known Issues

Master Answer Record: 68767

All Vivado IP Change Logs

Master Vivado IP Change Logs: 72775

Xilinx Support web page

Notes:

1. For a complete list of supported devices, see the Vivado IP catalog.

2. Standalone driver details can be found in the Vitis directory (<install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm). For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.