Ensure that all the timing constraints for the core were properly incorporated from the example design and that all constraints were met during implementation.
• Does it work in post-place and route timing simulation? If problems are seen in hardware but not in timing simulation, this could indicate a PCB issue. Ensure that all clock sources are active and clean.
• Check MMCM lock and PLL lock signal(s) are asserted.
• Verify the I/O pin planning and XDC constraints.
• Follow recommended reset sequence.
• Verify all clocks are connected and that the frequencies are as expected.
• Enable the AXI4-Lite based register interface to get core status and control.
• Make sure that the serial line trace lengths are equal.
• Verify the FMC_VADJ voltage is 1.8V for FMC card use.