The interrupt enable register allows you to selectively generate an interrupt at the output port for each error/status bit in the ISR. An IER bit set to 0 does not inhibit an error/status condition from being captured, but inhibits it from generating an interrupt.
|
Bits |
Name |
Access |
Default Value |
Description |
|---|---|---|---|---|
|
31:11 |
Reserved |
RO |
0 |
Set bits in this register to 1 to generate the required interrupts. Set to 0 to disable the interrupt.
For a description of the specific interrupt you are enabling/disabling in this register see the ISR descriptions in Table: ISR Bit Mapping.
|
|
10 |
UNDERFLOW_IE |
R/W |
0 |
|
|
9 |
OVERFLOW_IE |
R/W |
0 |
|
|
8 |
AXI4S_VID_LOCK_IE |
R/W |
0 |
|
|
7:3 |
Reserved |
RO |
0 |
|
|
2 |
VSYNC_VALID_IE |
R/W |
0 |
|
|
1 |
TX_CE_ALIGN_ERR_IE |
R/W |
0 |
|
|
0 |
GTTX_RSTDONE_IE |
R/W |
0 |