Interrupt Status Register (ISR) (0x10) - 2.0 English

PG289 SMPTE UHD-SDI TX Subsystem

Document ID
PG289
Release Date
2022-10-19
Version
2.0 English

The interrupt status register captures the error and status information for the IP core.

Table 2-17:      ISR Bit Mapping

Bits

Name

Access(1)

Default
Value

Description

31:11

Reserved

RO

0

Reserved

10

UNDERFLOW_INTR

R/W1C

0

AXI4-Stream to Video out core underflow indication. This bit is enabled for the AXI4-Stream interface.

9

OVERFLOW_INTR

R/W1C

0

AXI4-Stream to Video out core overflow indication. This bit is enabled for the AXI4-Stream interface.

8

AXI4S_VID_LOCK_INTR

R/W1C

0

Lock indication from AXI4-Stream to Video out core. This bit is enabled for the AXI4-Stream interface.

7:3

Reserved

RO

0

Reserved

2

VSYNC_VALID_INTR

R/W1C

0

Asserted when Video sync has been detected at the start of each frame.

1

TX_CE_ALIGN_ERR_INTR

R/W1C

0

This bit indicates problems with the 5/6/5/6 clock cycle cadence of the tx_sd_ce input in SD-SDI mode. In SD-SDI mode, the tx_sd_ce signal must follow a regular 5/6/5/6 clock cycle cadence. If it does not, the SD-SDI serial stream is formed incorrectly. The TX_CE_ALIGN_ERR_INTR bit goes High if the cadence is incorrect.

0

GTTX_RSTDONE_INTR

R/W1C

0

Asserted when GTTX_RESETDONE is High

Notes:

1.W1C – Write 1 to Clear (to clear register bit, write 1 to the corresponding bit).