MODULE_CTRL Register (0x04) - 2.0 English

PG289 SMPTE UHD-SDI TX Subsystem

Document ID
PG289
Release Date
2022-05-18
Version
2.0 English

The module control register allows you to control the SMPTE UHD-SDI TX IP core and to change the IP core functional modes.

Table 2-15: MODULE_CTRL Register Bit Mapping

Bits

Name

Access

Default
Value

Description

31:25

Reserved

RO

0

Reserved

24

TX_ST352_STR_SWITCH_3G_A

R/W

0

When this is set to 1'b1, the ST352 value from the TX_ST352_DATA_DS2 register (0x70 offset) is used instead of TX_ST352_DATA_DS3 (0x20 offset)

23

TX_INSERT_C_STR_ST352

R/W

0

This bit controls whether ST352 has to be inserted into the channel C stream. Contents of registers from offset, 0x70 to 0x8C are used for the ST352 payload

22:21

FMT_SEL

R/W

0

YCbCr 444, YCbCr 422, or YCbCr 420 color space selection

2'b00 : YCbCr 422 format
2'b01 : YCbCr 420 format
2'b10 : YCbCr 444 format

This field is not enabled for Native SDI interface.

20

TX_INSERT_EDH

R/W

0

When this bit is High, the transmitter generates and inserts EDH packets into every field in SD-SDI mode.

When this bit is Low, EDH packets are not inserted. This bit is ignored in all modes except SD-SDI mode.

19

TX_INSERT_LN

R/W

0

When this bit is High, the transmitter inserts line numbers into all active data streams after the EAV of each video line. The line numbers must be supplied on the tx_line_ch n input ports of all active data stream pairs.

When this bit is Low, line numbers are not inserted. This bit is ignored in SD-SDI mode.

18

TX_USE_ANC_IN

R/W

0

When Low, the data streams out of the ST352 packet insertion function are routed internally to the TX output channels. When High, the TX output channels accept data streams from the tx_ds[16:1]_anc_in ports.

17

TX_SD_BITREP_BYPASS

R/W

0

This bit bypasses the 11 times bit replicator used in SD-SDI mode when High. For normal operation with Xilinx serial transceiver transmitters, this input must be Low so that the bit replicator function is active.

16

TX_INSERT_SYNC_BIT

R/W

0

In 6G and 12G modes, when this bit is High, the sync bit insertion function is enabled for run length mitigation.

15

TX_ST352_F2_EN

R/W

0

This bit controls whether or not ST 352 packets are inserted on the line indicated by tx_vpid_line_f2

14

TX_OVERWRITE_ST352

R/W

0

If this bit is High, ST 352 packets already present in the data streams are overwritten. If this bit is Low, existing ST 352 packets are not overwritten.

13

TX_INSERT_ST352

R/W

0

When this bit is High, ST 352 packets are inserted into the data streams, otherwise the ST352 packets are not inserted.

12

TX_INSERT_CRC

R/W

0

When this bit is High, the transmitter generates and inserts CRC values into the data streams for each video line in all modes except SD-SDI. When this bit is Low, CRC values are not inserted into the data streams. This bit is ignored in SD-SDI mode.

11

Reserved

RO

0

Reserved

10:8

TX_MUX_SEL

R/W

0

Internal TX mux pattern which specifies the data stream interleaving pattern to be used:

3’b000 : SD-SDI,HD-SDI,and 3G-SDI level A

3’b001 : 3G-SDI level B
3’b010 : 8 stream interleave in 6G-SDI and 12G-SDI modes
3’b011 : 4 stream interleave in 6G-SDI mode
3’bs100-16 stream interleave in 12G-SDI mode

7

TX_M

R/W

0

0 – integer frame rate

1 – fractional frame rate (frame_rate/1.001)

6:4

SDITX_SS_MODE

R/W

0

TX Mode

3’b000 : HD-SDI mode
3’b001 : SD-SDI mode
3’b010 : 3G-SDI mode Level A Mode if SDI TX bridge is enabled; 3G-SDI mode if SDI TX bridge is not enabled
3’b011: 3G-SDI Level B Mode if SDI TX bridge is enabled; NA if SDI TX bridge is not enabled

3’b100 : 6G-SDI mode
3’b101 : 12G-SDI mode

3

ENABLE_HFR

R/W

0

When this bit is 1,the resolutions transmitted is HFR

2:0

Reserved

RO

0

Reserved