Native SDI Signals - 2.0 English

PG289 SMPTE UHD-SDI TX Subsystem

Document ID
PG289
Release Date
2022-10-19
Version
2.0 English

These signals are available when the Video Interface is set to Native SDI in the Vivado IDE. The native SDI also supports an AXI4-Lite control interface. When the AXI4-Lite control interface is enabled, some ports are not available as noted in Table: Native SDI Signals. This configuration is similar to the transmitter of the SMPTE UHD-SDI IP core in terms of functionality, and therefore for further information, see the SMPTE UHD-SDI LogiCORE IP Product Guide (PG205) [Ref 6].

IMPORTANT:   In Native SDI mode, the image data values must be constrained to avoid SDI prohibited codes. You must avoid the values from 00h to 003h and 3FCh to 3FFh. In Native Video mode and AXI4-Stream mode, the image data values below 004h (000h to 003h) are clamped at 004h, and the values above 3FBh (3FCh to 3FFh) are clamped at 3FBh internally, to avoid the SDI prohibited codes.

Table 2-8:      Native SDI Signals

Signal

I/O

Description

sdi_tx_clk

I

SMPTE UHD-SDI TX core clock

sdi_tx_rst

I

Active-High reset

sdi_tx_ctrl[31:0](2)

I

Bit0: module_enable
Bit1: not used
Bit3–bit2: reserved
Bit6–bit4: tx_mode:(1)

000-HD
001-SD
010-3G
100-6G
101-12G;

Bit7: tx_m (tx_rate):

0 – integer frame rate
1 – fractional frame rate (frame_rate/1.001)

Bit10–bit8: tx_mux_pattern:

000-SD, HD, and 3G level A
001-3G level B
010-8 stream interleave in 6G and 12G
modes
011-4 stream interleave in 6G mode

Bit11: reserved
Bit12: tx_insert_crc
Bit13: tx_insert_st352
Bit14: tx_overwrite_st352
Bit15: tx_st352_f2_en
Bit16: tx_insert_sync_bit
Bit17: tx_sd_bitrep_bypass
Bit18: tx_use_anc_in
Bit19: tx_insert_ln
Bit20: tx_insert_edh
Bit23: tx_insert_c_str_st352
Bit24: st352_str_switch_3g_a
Bit31–bit25: reserved

ST352_DATA_IN_tx_st352_data_ch0[31:0](2)

I

ST352 data for Y stream of channel 0

ST352_DATA_IN_tx_st352_data_ch1[31:0](2)

I

ST352 data for Y stream of channel 1

ST352_DATA_IN_tx_st352_data_ch2[31:0](2)

I

ST352 data for Y stream of channel 2

ST352_DATA_IN_tx_st352_data_ch3[31:0](2)

I

ST352 data for Y stream of channel 3

ST352_DATA_IN_tx_st352_data_ch4[31:0](2)

I

ST352 data for Y stream of channel 4

ST352_DATA_IN_tx_st352_data_ch5[31:0](2)

I

ST352 data for Y stream of channel 5

ST352_DATA_IN_tx_st352_data_ch6[31:0](2)

I

ST352 data for Y stream of channel 6

ST352_DATA_IN_tx_st352_data_ch7[31:0](2)

I

ST352 data for Y stream of channel 7

ST352_DATA_IN_C_tx_st352_data_ch0[31:0](2)(4)

I

ST352 data for C stream of channel 0

ST352_DATA_IN_C_tx_st352_data_ch1[31:0](2)(4)

I

ST352 data for C stream of channel 1

ST352_DATA_IN_C_tx_st352_data_ch2[31:0](2)(4)

I

ST352 data for C stream of channel 2

ST352_DATA_IN_C_tx_st352_data_ch3[31:0](2)(4)

I

ST352 data for C stream of channel 3

ST352_DATA_IN_C_tx_st352_data_ch4[31:0](2)(4)

I

ST352 data for C stream of channel 4

ST352_DATA_IN_C_tx_st352_data_ch5[31:0](2)(4)

I

ST352 data for C stream of channel 5

ST352_DATA_IN_C_tx_st352_data_ch6[31:0](2)(4)

I

ST352 data for C stream of channel 6

ST352_DATA_IN_C_tx_st352_data_ch7[31:0](2)(4)

I

ST352 data for C stream of channel 7

ST352_DATA_IN_tx_st352_line_f1

I

Odd line to insert ST352 data. This is used for
progressive video and you have to control the
tx_st352_f2_en bit of the sdi_tx_ctrl bus.(1)

ST352_DATA_IN_tx_st352_line_f2

I

Even line to insert ST352 data

SDI_DS_IN_ds1[9:0]

I

SDI data stream 1

SDI_DS_IN_ds2[9:0]

I

SDI data stream 2

SDI_DS_IN_ds3[9:0]

I

SDI data stream 3

SDI_DS_IN_ds4[9:0]

I

SDI data stream 4

SDI_DS_IN_ds5[9:0]

I

SDI data stream 5

SDI_DS_IN_ds6[9:0]

I

SDI data stream 6

SDI_DS_IN_ds7[9:0]

I

SDI data stream 7

SDI_DS_IN_ds8[9:0]

I

SDI data stream 8

SDI_DS_IN_ds9[9:0] to SDI_DS_IN_ds16[9:0](4)

I

SDI data stream 9 to 16

SDI_DS_IN_ln_num_1[10:0] to
SDI_DS_IN_ln_num_4[10:0]

I

SDI data stream line number 1 to 4

SDI_DS_IN_ln_num_5[10:0] to
SDI_DS_IN_ln_num_8[10:0](4)

I

SDI data stream line number 5 to 8

SDI_DS_IN_tx_ce

I

Clock enable

SDI_DS_IN_tx_sd_ce

I

SD-SDI mode clock enable

sdi_tx_err[31:0](2)

O

Bit0: tx_ce_align_err
Bit31 to bit1: Reserved

Notes:

1.See the TX Ports section of the SMPTE UHD-SDI LogiCORE IP Product Guide (PG205) [Ref 6] for more details on the signal descriptions.

2.Enabled only when the Enable AxiLite interface option is not selected in the Vivado IDE.

3.Enabled only when the Insert ST352 in C stream option is selected in the Vivado IDE.

4.Enabled only when Native SDI is selected as the video interface and 12G SDI 16DS is selected as the SDI standard.