The core control register allows you to enable and disable the
SMPTE UHD-SDI TX
IP core and apply a soft reset during core operation.
Table 2-14:
RST_CTRL Register Bit Mapping
|
Bits
|
Name
|
Access
|
Default
Value
|
Description
|
|
31:10
|
Reserved
|
RO
|
0
|
Reserved
|
|
9
|
AXI4S_VID_OUT_EN
|
R/W
|
0
|
Enable bits for AXI4-Stream to Video out core
1 – AXI4-Stream to Video out core is enabled
0 – AXI4-Stream to Video out core is disabled.
This bit is enabled only for the AXI4-Stream interface and has no impact on native video and native SDI interface subsystem configurations.
|
|
8
|
SDITX_BRIDGE_EN
|
R/W
|
0
|
Enable bits for SDI TX Bridge
1 – SDI TX Bridge is enabled
0 – SDI TX Bridge is disabled
This bit is not enabled for the native SDI interface subsystem.
|
|
7:2
|
Reserved
|
RO
|
0
|
Reserved
|
|
1
|
SRST
|
R/W
|
0
|
Soft reset for SDI TX IP core
If 1 is written to this bit, all registers of the SDI TX IP core are reset.
|
|
0
|
SDITX_IP_EN
|
R/W
|
0
|
Enable bits for SDI TX IP core
1 – SDI TX IP core is enabled
0 – SDI TX IP core is disabled
|