Register Space - 2.0 English

PG289 SMPTE UHD-SDI TX Subsystem

Document ID
PG289
Release Date
2022-05-18
Version
2.0 English

This section details registers available in the SMPTE UHD-SDI TX Subsystem . The address map is split into following regions:

SMPTE UHD-SDI TX core

Video Timing Controller (VTC) core

The VTC core is enabled only for the AXI4-Stream interface configuration. Each IP core is given an address space of 64K. Example offset addresses from the system base address when the SMPTE UHD-SDI TX and VTC core registers are enabled are shown in Table: Subcore Address Offsets .

Table 2-12: Subcore Address Offsets

IP Core

Offset

SMPTE UHD-SDI TX

0x0_0000

VTC

0x1_0000