Reset - 2.0 English

PG289 SMPTE UHD-SDI TX Subsystem

Document ID: PG289
Release Date: 2022-10-19
Version: 2.0 English

Table: Core reset, and Interface to the Transceiver Ports provides details about the core reset, and Interface to the Transceiver Ports

Table A-4: Core reset, and Interface to the Transceiver Ports
Signal	Direction	Description
RESET_I	Input Synchronous reset	Active-High. Needs 8 clock cycles to reset correctly
DRPEN_O	Output	Unused. Leave floating
DRPWEN_O	Output	Unused. Leave floating
DRPDO_I[15:0]	Input	Unused. Connect to 0 or 1
DRPDATA_O[15:0]	Output	Unused. Leave floating
DRPADDR_O[8:0]	Output	Unused. Leave floating
DRPRDY_I	Input	0 Unused. Connect to 0 or 1

Table A-5: DRP User Port (Unused)
Signal	Direction	Description
DRP_USER_REQ_I	Input	Unused. Connect to 0.
DRP_USER_DONE_I	Input	Unused. Connect to 0.
DRPEN_USER_I	Input	Unused. Connect to 0.
DRPWEN_USER_I	Input	Unused. Connect to 0.
DRPADDR_USER_I[8:0]	Input	Unused. Connect to 0.
DRPDATA_USER_I[15:0]	Input	Unused. Connect to 0.
DRPRDY_USER_O	Output	Unused. Leave floating.
DRPDATA_USER_O[15:0]	Output	Unused. Leave floating.
DRPBUSY_O	Output	Unused. Leave floating.

Table A-6: TXPI Ports
Signal Name	Direction	Description
ACC_DATA[4:0]	Output	Connect to TXPIPPMSTEPSIZE[4:0] of the transceiver.

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Table A-7: Debug Port
Signal	Direction	Description
ERROR-O[20:0]	Output	Output of phase detector. Signed number.
VOLT_O[21:0]	Output	Output of low-pass filter. Signed number.
DRPDATA_SHORT_O[7:0]	Output	Unused. Leave floating.
CE_PI_O	Output	Clock enable for accumulator.
CE_PI2_O	Output	Clock enable for low pass filter and DAC.
CE_DSP_O	Output	Reset phase detector counters, load phase detector error into the low-pass filter.
OVF_PD	Output	Overflow in phase detector.
OVF_AB	Output	Saturation of the low-pass filter inputs.
OVF_INT	Output	Saturation of the low-pass filter integrator.
OVF_VOLT	Output	Saturation of the low-pass filter output.

Table A-8: PICXO Loop Parameters
Signal	Direction	Description
G1[4:0]	Input	Filter linear path gain: range 0 to x12h.
G2[4:0]	Input	Filter integrator path gain: range 0 to x14h.
R[15:0]	Input	Reference divider: range 0 to 65535. Divides by R+2.
V[15:0]	Input	TXOUTCLK_I divider: range 0 to 65535. Divides by V+2.
ACC-STEP[3:0]	Input	PICXO step size: range 1 to 15 (0=no step).
CE_DSP_RATE[15:0]	Input	DSP divider: default 07FF. Control CE_DSP rate.
VSIGCE_I	Input	Clock enable to the TXOUTCLK_I divider. Connect to 1 for normal operation.
VSIGCE_O	Output	Reserved: Floating.
RSIGCE_I	Input	Clock enable of Reference divider. Connects to 1 for normal operation.
C_I[7:0]	Input	Reserved. Connect to 0.
P_I[9:0]	Input	Reserved. Connect to 0.
N_I[9:0]	Input	Reserved. Connect to 0.
OFFSET_PPM[21:0]	Input	Direct frequency offset control. Signed number. OFFSET_PPM overwrites the output of the low-pass filter (VOLT_O) when OFFSET_EN is High.
OFFSET_EN	Input	Enable direct frequency offset control input. Active-High: Enables OFFSET_PPM input to overwrite output of low-pass filter (Volt).
HOLD	Input	Hold low-pass filter output value (Volt). Clock enable of Volt that stops Volt to the latest known ppm.
DON_I	Input	Dither On. Potential jitter reduction. Active-High.