The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
10/19/2022 |
2.0 |
Updated Unsupported Features, Native SDI Signals, and Native Video (VID_IO_IN) Interface Signals sections. |
|
05/18/2022 |
2.0 |
Editorial changes. |
|
04/26/2022 |
2.0 |
Added parameters to select HFR and YCbCr444 support to reduce resource count. |
|
06/30/2021 |
2.0 |
•Added HFR Support for 10-bit 6G/12G mode at AXI Interface Subsystem Level •Updated Unsupported Features section •Updated module control register description for HFR •Added PICXO FRACXO IP Core for PICXO IP in Appendix A |
|
01/11/2021 |
2.0 |
•Added Versal ACAP support. •Added Versal ACAP Block Automation in UHD-SDI TX Subsystems section. •Added new Programming Sequence section. •Updated Unsupported Features section. •Updated Compiling Software in the Vitis Software Platform section. |
|
11/18/2020 |
2.0 |
Added Support for HLG HDR in IP Facts section. |
|
09/15/2020 |
2.0 |
•Updated 12-bit and HFR support in the following sections: •Updated Clocking section in the Example Design chapter. •Updated Clocking section in the Designing with the Core chapter. •Added information on CPLL-QPLL usage for 12G SDI in the CPLL Clocking section. |
|
06/14/2019 |
2.0 |
Updated This Figure. |
|
12/05/2018 |
2.0 |
•SMPTE 352: Payload packet insertion of Y stream and C stream supported •Application Example Design Tab added •ZCU106 UHD-SDI Pass-Through with PICXO Example Design Example Design added •PICXO FRACXO IP Core added |
|
04/04/2018 |
2.0 |
•Added Native Video and Native SDI interfaces •Added YCbCr420 format feature details |
|
10/04/2017 |
1.0 |
Initial Xilinx release. |