The
SMPTE UHD-SDI TX
registers are available when
Enable AXI4-Lite Interface
is selected in the Vivado IDE. The
SMPTE UHD-SDI TX
IP core register space is shown in
Table: SMPTE UHD-SDI TX IP Core Register Space
.
IMPORTANT:
This memory space must be aligned to an AXI word (32-bit) boundary.
All registers are in little endian format as shown in
This Figure
.
Figure 2-2:
32-bit Little Endian Example
|
X-Ref Target - Figure 2-2
|
Table 2-13:
SMPTE UHD-SDI TX
IP Core Register Space
|
Offset
|
Name
|
Width
|
Access
|
Description
|
|
0x00
|
RST_CTRL
|
32-bit
|
R/W
|
Enable and soft reset controls for the IP core
|
|
0x04
|
MODULE_CTRL
|
32-bit
|
R/W
|
Module control register
|
|
0x08
|
RESERVED
|
32-bit
|
N/A
|
N/A
|
|
0x0C
|
GLBL_IER
|
32-bit
|
R/W
|
Global interrupt enable register
|
|
0x10
|
ISR
|
32-bit
|
R/W1C
|
Interrupt status register
|
|
0x14
|
IER
|
32-bit
|
R/W
|
Interrupt enable register
|
|
0x18
|
TX_ST352_LINE
|
32-bit
|
R/W
|
ST352 packet insertion line number
|
|
0x1C
|
TX_ST352_DATA_DS1
|
32-bit
|
R/W
|
Data stream 1 ST352 packet data
|
|
0x20
|
TX_ST352_DATA_DS3
|
32-bit
|
R/W
|
Data stream 3 ST352 packet data
|
|
0x24
|
TX_ST352_DATA_DS5
|
32-bit
|
R/W
|
Data stream 5 ST352 packet data
|
|
0x28
|
TX_ST352_DATA_DS7
|
32-bit
|
R/W
|
Data stream 7 ST352 packet data
|
|
0x2C
|
TX_ST352_DATA_DS9
|
32-bit
|
R/W
|
Data stream 9 ST352 packet data
|
|
0x30
|
TX_ST352_DATA_DS11
|
32-bit
|
R/W
|
Data stream 11 ST352 packet data
|
|
0x34
|
TX_ST352_DATA_DS13
|
32-bit
|
R/W
|
Data stream 13 ST352 packet data
|
|
0x38
|
TX_ST352_DATA_DS15
|
32-bit
|
R/W
|
Data stream 15 ST352 packet data
|
|
0x3C
|
VERSION
|
32-bit
|
RO
|
Version Register
|
|
0x40
|
SS_CONFIG
|
32-bit
|
RO
|
IP core Configuration
|
|
0x68
|
SDI_TX_BRIDGE_STS
|
32-bit
|
RO
|
SDI TX Bridge Status
|
|
0x6C
|
AXI4S_VID_OUT_STS
|
32-bit
|
R/W
|
AXI4-Stream Video Out status register
|
|
0x70
|
TX_ST352_DATA_DS2
|
32-bit
|
R/W
|
Data stream 2 ST352 packet data
|
|
0x74
|
TX_ST352_DATA_DS4
|
32-bit
|
R/W
|
Data stream 4 ST352 packet data
|
|
0x78
|
TX_ST352_DATA_DS6
|
32-bit
|
R/W
|
Data stream 6 ST352 packet data
|
|
0x7C
|
TX_ST352_DATA_DS8
|
32-bit
|
R/W
|
Data stream 8 ST352 packet data
|
|
0x80
|
TX_ST352_DATA_DS10
|
32-bit
|
R/W
|
Data stream 10 ST352 packet data
|
|
0x84
|
TX_ST352_DATA_DS12
|
32-bit
|
R/W
|
Data stream 12 ST352 packet data
|
|
0x88
|
TX_ST352_DATA_DS14
|
32-bit
|
R/W
|
Data stream 14 ST352 packet data
|
|
0x8C
|
TX_ST352_DATA_DS16
|
32-bit
|
R/W
|
Data stream 16 ST352 packet data
|
|
Notes:
1.
Access type and reset value for all the reserved bit in the registers is read-only with value 0.
2.
Register accesses should be word aligned and there is no support for a write strobe. WSTRB is not used internally.
3.
Only the lower 7 (6:0) of the read and write address of the AXI4-Lite interface are decoded. This means that
accessing addresses 0x00 and 0x80 results in reading the same address as 0x00.
4.
Reads and writes to addresses outside this table do not return an error.
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