Transceiver (GT) Clocking - 2.0 English

SMPTE UHD-SDI TX Subsystem (PG289)

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Note: For AMD Versal™ Adaptive SoC GT clocking information, refer to the Versal Adaptive SoC GTY Transceivers Architecture Manual [Ref 19] .

Make sure QPLL is getting reset before starting the IP.

Monitor the QPLL LOCK signal.

Verify that QPLL input clock frequency is of expected value.

It is mandatory to reset the QPLL if clock input to QPLL is stopped or unstable. See
AR 57738 for debugging transceiver reference clock issues.

Make sure to use QPLL default settings from latest GT Wizard IP core based on target device.

Check the voltage rails on the transceivers. See AR 57737 for more information.

Measure TXOUTCLK and ensure that it is the expected frequency.

Make sure the transceiver TXOUTCLK is the clock driving tx_usrclk , TXUSRCLK , and TXUSRCLK2 .

Monitor TXBUFFSTATUS[2:0] for overflow and underflow errors.