Video-Over-AXIS Interface Signals - 2.0 English

SMPTE UHD-SDI TX Subsystem (PG289)

Document ID
PG289
Release Date
2023-05-16
Version
2.0 English

These signals are available when the Video Interface is set to AXI4-Stream in the AMD Vivado™ IDE.

Table 2-3: Video-Over-AXIS Interface Signals

Signal

I/O

Description

video_in_clk

I

Video input clock.

video_in _arstn

I

Video input active-Low synchronous reset.

VIDEO_IN_tdata[n-1:0]

O

Video input data for carrying YCbCr 4:4:4 / YCbCr 4:2:2 / YCbCr 4:2:0 video with 10 or 12-bit per component, based on the color depth configuration.
For 10bpc, n=64

For 12bpc, n=72

(For details see the AXI4-Stream to Video Out Product Guide (PG044) [Ref 7] (AXI4-Stream Data Interface Signal Descriptions).

VIDEO_IN_tlast

O

AXI4-Stream TLAST. End of Line.

VIDEO_IN_tready

I

AXI4-Stream TREADY.

VIDEO_IN_tuser

O

AXI4-Stream TUSER. Start of Frame.

VIDEO_IN_tvalid

O

AXI4-Stream TVALID. Active video data enable.

fid

O

Field ID for interlaced videos, fid toggles based on the selected field:
0- even field
1- odd field
For progressive videos, fid is set to 0.

Note: fid is expected to toggle in case of psf and 3G-level B progressive videos, as in these modes, one progressive frame is split into two fields. These two fields are transported independently, similar to interlaced video, and again combined and correctly paired together at receiver side with the help of fid signal to construct the original progressive frame.

For example, when 1080p 60 Hz video is transported on 3G-SDI level B-DL, the video transport is actually 1080i 60 Hz. The transport is interlaced, but the picture is progressive.