The UHD-SDI pass-through with the phase interpolator controlled crystal oscillator (PICXO) example design is built using the SMPTE UHD-SDI TX and RX Subsystems. Video or image data is received and processed by the UHD-SDI RX Subsystem. An AXI4-Stream FIFO is used for synchronization and temporary storage between the UHD-SDI RX Subsystem and the UHD-SDI TX Subsystems. The SMPTE UHD-SDI TX Subsystem transmits SDI data from the AXI4-Stream FIFO after the application programs the SMPTE UHD-SDI TX Subsystem sub-core registers based on the received SDI stream and the ST-352 payload packet data. The system is designed to replace external voltage-controlled crystal oscillator (VCXO) circuits by using functionality within each serial gigabit transceiver. For information on PICXO, see the All Digital VCXO Replacement for Gigabit Transceiver Applications (XAPP1241) [Ref 17] .
Each transceiver has a phase interpolator (PI) circuit in the high-speed analog PLL output circuits that provides, on an individual transceiver channel basis, the ability to phase and frequency modulate the transmit clock operating the transceiver. Using a fully digital interface, the phase interpolator can be phase and frequency controlled from the device logic resources under control of a high-resolution programmable digital PLL. In conjunction with the device logic digital PLL, the phase interpolator provides the ability to phase or frequency modulate the transceiver data output directly locking to an input reference pulse or clock while providing a built-in clock cleaning filter function.
The example design application software runs on the AMD Zynq ™ UltraScale+ ™ MPSoC Arm™ processor subsystem (PS) and is fully software-controlled. (For simplicity, the PS is not shown in This Figure .)