In this mode, up to 32 channels of audio can be extracted by the UHD-SDI Audio (Extract) IP. Channels 1 and 2 of the extracted audio are sent to the SPDIF/AES3 TX IP for AES playback.
The Audio Clock Recovery (ACR) IP is used to generate the audio sample rate clock (48 kHz, 44.1 kHz, or 32 kHz) from the SDI RX video clock. Application software programs the N and CTS values in the ACR IP, based on the SDI RX mode and the audio sample rate provided by the UHD-SDI Audio (Extract) IP. The ACR IP tracks the SPDIF/AES3 TX FIFO data count to adjust the sample rate clock to avoid FIFO overflow or underflow resulting in dropping or insertion of null samples. The sample rate clock from the ACR is fed to the on-board PLL for generating the audio clock (F s *512) for the SPDIF/AES3 TX IP. On the other hand, Audio captured from the AES input is embedded on to the SDI TX.
The example design application software runs on the Zynq UltraScale+ MPSoC Arm processor subsystem (PS) and is fully software controlled.