AXI4-Lite Interface Ports - 2.0 English

SMPTE UHD-SDI Receiver Subsystem Product Guide

Document ID
PG290
Release Date
2022-04-26
Version
2.0 English

These signals are enabled when the AXI4-Lite interface option is selected.

Table 2-1: AXI4-Lite Interface Port Descriptions

Signal

I/O

Description

s_axi_aclk

I

AXI4-Lite clock

s_axi_arstn

I

AXI4-Lite reset. Active-Low

S_AXI_CTRL*

AXI4-Lite interface, defined in the Vivado Design Suite: AXI Reference Guide (UG1037) [Ref 16] .