AXI4-Lite Interfaces - 2.0 English

SMPTE UHD-SDI Receiver Subsystem Product Guide

Document ID
PG290
Release Date
2022-04-26
Version
2.0 English

Read from a register that does not have all 0s as a default to verify that the interface is functional. See This Figure and This Figure . Output s_axi_arready asserts when the read address is valid, and output s_axi_rvalid asserts when the read data/response is valid. If the interface is unresponsive, ensure that the following conditions are met:

The s_axi_aclk and aclk inputs are connected and toggling.

The interface is not being held in reset, and s_axi_areset is an active-Low reset.

The interface is enabled, and s_axi_aclken is active-High (if used).

The main core clocks are toggling and that the enables are also asserted.

If the simulation has been run, verify in simulation and/or a debug feature capture that the waveform is correct for accessing the AXI4-Lite interface.

Figure B-2: Read

X-Ref Target - Figure B-2

Figure_3-17_AXI-4_Lite_Read.jpg
Figure B-3: Write

X-Ref Target - Figure B-3

Figure_3-16_AXI-4_Lite_Write.jpg