AXI4-Stream (Video) Interface Ports - 2.0 English

SMPTE UHD-SDI Receiver Subsystem Product Guide

Document ID
PG290
Release Date
2022-04-26
Version
2.0 English

These signals are enabled when the AXI4-Stream option is selected for the video interface.

Table 2-2: Video-Over-AXIS Interface P ort Descriptions

Signal

I/O

Description

video_out_clk

I

Video output clock

video_out _arstn

I

Video output active-Low reset.

VIDEO_OUT_tdata [n-1:0]

O

Video data carrying YCbCr 4:4:4 / YCbCr 4:2:2 / YCbCr 4:2:0 video with 10 or 12-bit per component, based on the color depth configuration.

For 10bpc, n=64

For 12bpc, n=72

(For details see the AXI4-Stream Video IP and System Design (UG934) [Ref 8] )

VIDEO_OUT_tlast

O

AXI4-Stream TLAST. End of Line

VIDEO_OUT_tready

I

AXI4-Stream TREADY.

VIDEO_OUT_tuser

O

AXI4-Stream TUSER. Start of Frame

VIDEO_OUT_tvalid

O

AXI4-Stream TVALID. Active video data enable

fid

O

Field ID. Connected field of Video-in to AXI4 Stream IP.

For Interlaced videos, fid will toggle based on the field selected

0: Even field

1: Odd field

For Progressive videos- fid will be set as 0.

Note: The fid is expected to toggle in psf and 3G-level B progressive videos. In these modes, one progressive frame is split into two fields which are transported independently (similar to interlaced video) and then combined and correctly paired together at the receiver side with the help of the fid signal to construct the original progressive frame.

For example, when 1080p 60 Hz video is transported on 3G-SDI level B-DL, the video transport is actually 1080i 60 Hz – the transport is interlaced, but the picture is progressive.