Features - 2.0 English

SMPTE UHD-SDI Receiver Subsystem Product Guide
Document ID
PG290
Release Date
2022-04-26
Version
2.0 English

• Supported configurations:

° AXI4-Stream, Native Video, Native SDI data interfaces

° 2 Pixels per clock (PPC)

° 10 bit, 12 bits per color component

° YCbCr/RCB 4:4:4, YCbCr 4:2:2, YCbCr 4:2:0 color spaces

° Block automation for Versal™ ACAP device family

• High Frame Rates at Native SDI

• 6G/12G 10 bit High Frame Rates Support for AXI stream RX Subsystem configurations

• AXI4-Lite interface for register access to configure different subsystem options

• Audio support

• Supports HLG HDR video

• Standards compliance:

° SMPTE ST 259: SD-SDI at 270 Mb/s

° SMPTE RP 165: EDH for SD-SDI

° SMPTE ST 292: HD-SDI at 1.485 Gb/s and 1.485/1.001 Gb/s

° SMPTE ST 372: Dual Link HD-SDI

° SMPTE ST 424: 3G-SDI with data mapped by any ST 425-x mapping at 2.97 Gb/s and 2.97/1.001 Gb/s

° SMPTE ST 2081-1: 6G-SDI with data mapped by any ST 2081-x mapping at 5.94 Gb/s and 5.94/1.001 Gb/s

° SMPTE ST 2082-1: 12G-SDI with data mapped by any ST 2082-x mapping at 11.88 Gb/s and 11.88/1.001 Gb/s

° Dual link and quad link 6G-SDI and 12G-SDI supported by instantiating two or four SMPTE UHD-SDI RX subsystems

° SMPTE ST 352: Payload ID packets

• Designed and supported to work directly with the UHD-SDI GT core [Ref 18]

• Supports Versal ACAP (GTYE5) product family

LogiCORE IP Facts Table

Core Specifics

Supported Device Family (1)

UltraScale+™ (GTHE4, GTYE4)

Versal™ ACAP (GTYE5, GTYP)

Zynq® UltraScale+ MPSoC (GTHE4, GTYE4)

Zynq UltraScale+ RFSoC

Supported User Interfaces

AXI4-Lite, AXI4-Stream,
native video, and native SDI

Resources

Performance and Resource Utilization web page

Provided with Core

Design Files

Hierarchical subsystem packaged with

SMPTE UHD-SDI RX core and other IP cores

Example Design

Vivado® IP integrator

Test Bench

N/A

Constraints File

IP cores delivered with XDC files

Simulation Model

N/A

Supported
S/W Driver (2)

Standalone and Linux

Tested Design Flows (3)

Design Entry

Vivado® Design Suite

Simulation

For supported simulators, see the
Xilinx Design Tools: Release Notes Guide .

Synthesis

Vivado® Synthesis

Support

Release Notes and Known Issues

Master Answer Record: 68766

All Vivado IP Change logs

Master Vivado® IP Change Logs: 72775

Xilinx Support web page

Notes:

1. For a complete list of supported devices, see the Vivado® IP catalog.

2. Standalone driver details can be found in the Vitis™ directory (<install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm). Linux OS and driver support information is available from
http://www.wiki.xilinx.com/Xilinx+V4L2+SDI+Rx+driver.

3. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.